When the semiconductor industry began the transition from 200-mm wafers to 300-mm wafers more than a decade ago, chip makers convinced tool suppliers to foot the bill for the R&D required to make the move with the promise that they would be justly and richly rewarded with robust sales of the new systems, which much of the industry appeared anxious to adopt. But they were left holding the bag when the dot come bubble burst and—surprise—chip makers decided to delay deployment of 300-mm capacity.
Many equipment industry executives were understandably bitter about this. This was in large part the reason that, when chip makers first began making noise about moving to 450-mm wafers a few years ago, the sound you heard was mostly echos and crickets chirping.
A lot of people were skeptical right from the beginning that 450-mm would happen at all. Now it appears that 450-mm is inevitable, though the conventional wisdom holds that only a handful of chip makers—notably Intel Corp., Samsung Electronics Co. Ltd., Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Globalfoundries Inc.—will ever build 450-mm manufacturing lines.
Still, right from the start, there has been much debate about how tool suppliers and their customers would divvy up the R&D costs associated with moving to the new wafer size. (Bob Johnson of Gartner Inc. said this week that the cumulative cost of 450-mm development will be about $17 billion, about $2 billion of which is being spent this year, though he acknowledged that other estimates vary widely).
Some fledgling development efforts are now well underway, including the Global 450 Consortium, a $4.8 billion collaborative effort housed at the Albany NanoTech Complex and backed by the companies mentioned above, as well as IBM Corp.
For some tool makers, though, this was not enough. ASML Holding NV, the dominant player in lithography equipment, was largely seen dragging its feet on 450-mm. Moving to 450-mm will require new lithography equipment with more advanced stages that can support the increased size and weight without creating vibrations that would make accurate lithography exposure impossible. Given the fact that no more than a handful of chip makers are expected to buy the new tools, ASML foresaw a limited return on the considerable investment that would be required.
ASML of course has now come around, but only after the firm devised an innovative equity-plus-research funding scheme that asks those chip makers with the most to gain from the move to 450-mm wafers—and extreme ultraviolet (EUV) lithography that matter—to foot some of the bill for new technology up front.
On Monday, Intel announced it would acquire a 15 percent stake in ASML as part of a $4.1 billion deal to accelerate the development of 450-mm and EUV lithography. In addition to paying over $3 billion for the stake in ASML, Intel is also contributing more than $1 billion more directly to the development of the new technologies. Intel, of course, also committed to advanced purchase orders for 450-mm and EUV development and production tools.
@sprite0022: Great comment! In a tiny market like EUV litho tools, or DW Ebeam, a monopoly is appropriate. There are better uses for this kind of investment money. Kudo's to Nikon and Canon for dropping out of the advanced litho game for DSRL's!
I think that both TriGate and TSV's are 3-D technolgies. Back to the basics of Moore's law - reduction of the area of the transistor and the cells used for creating microelectornics devices will reduce the cost of the manufactring. There are side benfits of potential increase in speed and reduced energy per switching action that can be capture through this effort. Moore's law will end due to laws of physiscs ( how small can switching device get). As part of getting closer to the the physics limit - there is need for more vertical structures to provide the finctionality needed to reduce space. In the previous 15-20 years it was by adding metal layers; Then came incorporation of new materils into the stack that required more processing (layers = vertical additions). Now we are in Tri Gate and TSVs that again - allow to build "High Risers"in different ways ( condos's in the bottom floor, or simply put one strucutre on top of the other). However - we get to the point that the saving in silicon area in each new generation will be offset by the cost of additional processing. That is when Moore's law that we enjoyed it for the last 4 decades, stops- probably a bit before the absolute physical limitaion.
Once we get to 10-14 nm, multipatterning will be more established than wherever EUV is at. There should be no further revolutionary changes in the litho patterning.
If we're starting over on other than Si most likely some contact method like imprint or soft stamping lithography might be the new starting point, not optical projection.
Complementary litho is too expensive, maybe only intel could afford it. Pitch splitting combined with a second NGL exposure - slower, more expensive and more risky than either by itself.
LELE is more reasonable in near term.
It's also hard to wrap gate+oxide around a Si channel within 20 nm.
How can you make such wild statements with no facts?
Actually not just no facts, but actual nonsense.
No comapny can make billions in profit from selling a third of its output under cost unless subsidized by a government or "rich daddy"...Intel has neither:)
In fact I did publish a response taking responsibility for my error in the case of reporting on that TAITRA report. You can find it here.
The report by the Taiwan External Trade Development Council (TAITRA) quoted an anonymous source saying that TSMC's projected delivery of 3-D chips matches that of Intel, the world's biggest chip maker. Intel announced with great fanfare in May that it would begin high-volume production of 3-D chips using tri-gate transistors by the end of the year.
Did you ever correct this story ?
You never did -
and now you're commenting on ASML?
FYI Solid State has an excellent site:
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