ASML is willing to sell another 10 percent of the company to other chip makers who are willing to kick in for the development of 450-mm litho tools and EUV. The firm is currently in discussions with both Samsung and TSMC on taking a piece of the action. If those firms decline to participate, or agree to participate but don't collectively buy the entire 10 percent remaining that ASML is willing to sell, ASML will invite others to participate. (As a condition imposed by ASML, Intel's stake in the company is limited to a maximum of 15 percent.)
The whole thing is not unlike a waiter bringing the check before serving the meal. But it had to be this way. ASML was not going to put out the investment required on 450-mm without money up front. And owing to its dominant market share in leading-edge lithography tools, there will be no 450-mm chip production without ASML.
Intel has the most to gain from the move to 450-mm. Stacy Smith, the company's chief financial officer, said this week that it expects the move to 450-mm to save the company more than $10 billion in manufacturing costs. Still, Intel alone takes ASML up on its offer, its deep pockets will no doubt also benefit rivals who will then get access to 450-mm and EUV lithography tools.
That's where the 15 percent stake comes in. Even if Intel is the only chip firm to directly support ASML's development of these technologies, the world's biggest chip maker will get a piece of the action every time a rival pulls out its checkbook to buy one of the new tools. In the words of a spokesman for ASML, Intel now has real skin in the game and even more interest in seeing the development of these technologies succeed.
Whether Samsung, TSMC or any other chip vendor takes ASML up on its offer remains to be seen. On one hand, it can be argued, there is little incentive for them to do so at this point. Especially now that Intel has put its money where its mouth is, there is little doubt that ASML will develop 450-mm tools (though for EUV, the case is far from closed). Once ASML has the tools available, they will presumably be happy to sell them to Samsung, TSMC and anyone else who wants them and has the means to pay.
But Samsung and TSMC would be wise to pony up and get involved. When 450-mm tools become available, the leading-edge chip makers will want them ASAP. While there is no publicly disclosed intent to give Intel right of first refusal on new tools—other than those Intel has already committed to buying—come sense dictates that you take care of any part owners of your company before shopping them to the general public. If Samsung and TSMC don't get in on the ground floor, they may end up waiting until Intel is pretty sure it has all of the tools it wants before they get their hands on any.
Also, Intel's 15 percent stake in ASML—as well as any stake Samsung and TSMC may take—is in non-voting shares. But again, common sense dictates that the customer who is helping to foot the bill for the development of the technology will have a louder voice when it's time to make development decisions. Samsung, TSMC and any other firm that does not get in on the action may find itself outside looking in.
@sprite0022: Great comment! In a tiny market like EUV litho tools, or DW Ebeam, a monopoly is appropriate. There are better uses for this kind of investment money. Kudo's to Nikon and Canon for dropping out of the advanced litho game for DSRL's!
I think that both TriGate and TSV's are 3-D technolgies. Back to the basics of Moore's law - reduction of the area of the transistor and the cells used for creating microelectornics devices will reduce the cost of the manufactring. There are side benfits of potential increase in speed and reduced energy per switching action that can be capture through this effort. Moore's law will end due to laws of physiscs ( how small can switching device get). As part of getting closer to the the physics limit - there is need for more vertical structures to provide the finctionality needed to reduce space. In the previous 15-20 years it was by adding metal layers; Then came incorporation of new materils into the stack that required more processing (layers = vertical additions). Now we are in Tri Gate and TSVs that again - allow to build "High Risers"in different ways ( condos's in the bottom floor, or simply put one strucutre on top of the other). However - we get to the point that the saving in silicon area in each new generation will be offset by the cost of additional processing. That is when Moore's law that we enjoyed it for the last 4 decades, stops- probably a bit before the absolute physical limitaion.
Once we get to 10-14 nm, multipatterning will be more established than wherever EUV is at. There should be no further revolutionary changes in the litho patterning.
If we're starting over on other than Si most likely some contact method like imprint or soft stamping lithography might be the new starting point, not optical projection.
Complementary litho is too expensive, maybe only intel could afford it. Pitch splitting combined with a second NGL exposure - slower, more expensive and more risky than either by itself.
LELE is more reasonable in near term.
It's also hard to wrap gate+oxide around a Si channel within 20 nm.
How can you make such wild statements with no facts?
Actually not just no facts, but actual nonsense.
No comapny can make billions in profit from selling a third of its output under cost unless subsidized by a government or "rich daddy"...Intel has neither:)
In fact I did publish a response taking responsibility for my error in the case of reporting on that TAITRA report. You can find it here.
The report by the Taiwan External Trade Development Council (TAITRA) quoted an anonymous source saying that TSMC's projected delivery of 3-D chips matches that of Intel, the world's biggest chip maker. Intel announced with great fanfare in May that it would begin high-volume production of 3-D chips using tri-gate transistors by the end of the year.
Did you ever correct this story ?
You never did -
and now you're commenting on ASML?
FYI Solid State has an excellent site:
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.