Other EUV progress has also been reported in the past week:
• On source power: Nigel Farrar, vice president of technical marketing at Cymer, said Cymer has now achieved about 50 watt expose power on its HVM I source using a pre-pulse—which conditions the target prior to the main pulse—at full repetition rate using closed loop controls. (Back in February, Cymer also reported average power of 50 watts, but that was in open loop testing, minus the power-reducing controls placed on systems in the field to improve stability.)
• Meurice said the potential for 105 watts has been confirmed in lab experiments, supporting ASML's roadmap to volume production starting at 70 wafers per hour in 2014 and upgradable to 125 wafers per hour in 2016. He cautioned that in-situ experiments, as opposed to lab experiments, are still necessary to confirm this roadmap. Even if ASML stopped development now, Meurice said the lab data demonstrated that ASML's NXE:3300—the production tool successor to the pre-production NXE 3100 systems installed at several customer sites—would support throughput of 30 to 40 wafers per hour based on its superior architecture and energy efficiency. (Halting development, of course, is not the plan).
• Source availability: Farrar said Cymer's HVM I sources have been running at about 70 percent availability for the past two quarters, up from 50 percent in prior quarters. Only about 10 percent of the downtime was unscheduled, the rest was for planned maintenance.
• Source collector durability: Cymer has demonstrated stable reflectivity for its EUV source collector over more than 30 billion pulses. Collector reflectivity is a key issue because replacing the collector is a major undertaking and the collector's performance will degrade over time. Cymer does not know how long the source can last between replacements, but 30 billion pulses over more than a year is considered encouraging.
• Mask defectivity: Kalk acknowledged that EUV masks will not be defect-free. Due to the complexity involved, every EUV mask blank will have defects, an multi-layer mask blank defects cannot be repaired, Kalk said. But masks must be "defect free enough" to work, he said. In the case of memory, design patterns are redundant enough that the mask can be shifted and rotated accordingly in order to write the pattern around the defects—if mask makers know where they are, according to Kalk. Improvement in both blank and mask inspection tools, as well as mask writer accuracy, is required, Kalk said.
• Mask durability: No one will know exactly how long an EUV mask will last until they are used in high volume production. Kalk said different mask durability issues—including the appearance of haze on a mask and, later, mask absorber degratdation—arose in the first six years or so after the introduction of 193-nm lithography, depending on the number of exposures for a mask. "We are going to encounter issues," Kalk said. 'I don't even know what they are yet, but we are going to encounter them."
• Tools needed: The full tool kit for EUV masks won't be ready until about 2018, according to Kalk. He said development is needed on blank and mask inspection tools, as well as the Carl Zeiss EUV actinic aerial image metrology system (AIMS) for reticle defect and printability analysis. Kalk said that EUV insertion can occur before the full mask tool kit is in place, but that a "bridge strategy" will be required. As manufacturing eventually ramps up, new issues will arise he said.
The trouble with any scale-up solution such as this is the EUV power is a very small fraction of the total which is dominated by heat. The thermal loading at target EUV levels has not been comprehended.
Even since the article on July 9th saying they were "in talks with ASML", I haven't heard anything more about zPlasma (http://www.eetimes.com/electronics-news/4389852/EUV-startup-in-talks-with-ASML)
They believe they can have a 200W power source integrated into production equipment within four years for $5 million. Time will tell if this is actually possible, but at the very least they have a unique approach to the source problem.
This year Intel already raised the power requirement for EUV at 20 nm feature size (whatever node it is called) by a factor of several. Samsung knows the same issue for DRAM contacts at same size (shot noise). With this new awareness, the contingencies should be being accelerated in panic mode right now.
I doubt that we will see adoption of EUV as early as 2014. Even 2016 is not certain, but that's too far out to predict. My best guess is that EUV will happen eventually for a small group of companies that can justify the cost with high volumes, but there are other technologies now on the horizon that could supplant EUV or at least coexist with EUV for certain applications, or lower volumes where it would be difficult to amortize the cost of an EUV mask set.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.