As editor of the Memory Designline site, I'm always on the look out for research into memory technologies. Last week, the IEEE Spectrum published a piece on some work on flash memory being done by engineers at North Carolina State University (NCSU). The prototype design uses two floating point gates instead of one.
Here's how IEEE's writer sums it up: "Storing all of its charge on the bottom gate, the flash can act like its old nonvolatile self. But by using the second gate and a continuous source of power, it can work more quickly, shuffling preset proportions of charge between each of the gates to represent a 1 or a 0." The hope is that this technique could lead to instant-on computers. I've sent a note to the researchers to see if they might like to tell us more about their work.
For now, you can get more information by heading to the IEEE article , or the lead professor, Paul Franzon's web site .
If you have any thoughts or insights on this, please sound off below.
Some memory is not meant to be stored for a long time, but is supposed to be overwritten frequently (as in SRAM or DRAM). Other memory is meant to be stored indefinitely, but may not be read frequently (as in the SSD) or is read frequently (as in XiP or boot-up). The inherent conflicts of these requirements rules out the attractiveness of a memory that appears to satisfy all of them.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.