Next week is DVCon and there are five panels that I want to draw your attention to, two moderated by yours truly. I hope to see you there...
Next week is DVCon down in San Jose and with it there will be many great events to participate in. Panels tend to be a big draw and there are five that I want to bring to your attention. Two of them are official DVCon events and the other three are fringe events.
On Monday evening (6:30 till 9:00 in the Doubletree Hotel) Paul McLellan will be moderating the panel titled “Hardware/Software Co-design from a Software Perspective”. This is an EDAC event and features panelists Michael James, Senior Staff Engineer, Lockheed-Martin Space Systems Company, Atul Kwatra, Principal Engineer, Intel corporation, Bill Neifert, Chief Technology Officer, Carbon Design Systems and Don Williams, Head of Core Technology, Skype.
Bright and Early Tuesday morning (7:30 till 8:30 Pine/Cedar Ballroom) I will be moderating the panel titled “Do We Have What It Takes for Full-SoC Verification?” This panel will explore if the existing verification methodologies can scale to the full chip level and on the larger scale – what it actually mean to perform chip-level verification.
Later that day (2:30 till 3:30 in the Oak/Fir Ballroom) you will be able to savor the panel moderated by JL Gray or Verilab “The Resurgence of Chip Design”. Panelists include Ted Vucurevich - CEO of Enconcert, John Costello - VP of IC Design at Altera, Gary Smith - Founder and Chief Analyst at Gary Smith EDA, Jim Hogan - Founding Partner at Vista Ventures LLC and Victoria Colemann - VP, Emerging Platforms at Nokia.
On Wednesday (2:30 till 3:30 Oak/Fir Ballroom) I will be moderating the panel titled “Build or Buy: Which is the Best Practice for Hardware-Assisted Verification?” Panelists will be Albert Camilleri - Qualcomm, Inc. John Goodenough - ARM, Inc. Yu-Chin Hsu - SpringSoft, Inc. Peter Ryser - Xilinx, Inc. and Frank Schirrmeister - Cadence Design Systems, Inc.
If you are still around on Friday, then you can enjoy “Meet the Prototypers” (7:30 check in and breakfast 8:00 – 9:00 panel – Donner Ballroom) Kevin Morris will leads the discussion about FPGA-based prototyping and its importance for SoC and embedded software verification. Registration for this event is mandatory, as seating is limited.
I hope to see you in at least two of those. I will be taking names!
– keeping you covered
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