Many years ago and in a Galaxy that seems far far away, my buddy and journalism mentor Richard Goering teamed up to provide EDA coverage for EE Times...
Many years ago and in a Galaxy that seems far far away, my buddy and journalism mentor Richard Goering teamed up to provide EDA coverage for EE Times. When I joined EE Times back in 1997 to help Richard out on what was becoming an overwhelmingly active beat, Richard made it a point of pride to cover every, and I mean every, announcement that the EDA vendors made (and didn’t make). Needless to say, it was a hugely taxing job but a job we loved to do. Essentially, that meant that if I stepped out of the office to cover a conference, an EDAC meeting, a court battle or meet with a vendor, I better come back with a story. And in a news room, big news is the goal. Going to an event that didn’t have news to report was a waste of time. So that brings me to longtime EDA guru and market analyst Gary Smith. Gary was (and still is) a must go-to source on just about any EDA story. If you look at old stories, it’s hard to find a story from that era without a quote or two from Gary.
In addition to giving his insights into just about everything EDA, Gary, then the chief EDA analyst at Gartner Dataquest, also served as a visionary for what was needed to take the EDA industry and thus IC design to the next level. It was in about 1997 (or it may have been even earlier before I started covering the beat) when Gary started calling for the industry to produce what he coined as “ESL (Electronic System Level) tools” and this other idea called the “Silicon Virtual Prototype” or SVP.
As a bit of background, back in 1997, the VHDL versus Verilog wars had more or less come to a cease fire and the IC design industry had come to the conclusion that both languages could co-exist — in fact there was a new opportunity for vendors to make money offering dual language tools. And at that time, the industry was rallying around the concept of using IP as the way to fill those mammoth 100,000 gate designs that bleeding-edge .25-micron processes enabled. But Gary wasn’t satisfied with RTL languages and wanted the industry to produce a higher level language that would allow design teams to design at a C system level. Gary way back then had the insight that soon software would play a leading role in systems design and RT level co-design and co-verification and even the-way-before-it’s-time Synopsys’ Behavioral Compiler just wouldn’t cut it.
Then on top of that, Gary also called for what he coined the “Silicon Virtual Prototype.” The idea of this was to create an adjustable model of the hardware you were designing as a way to test your entire system design software and hardware together to make upfront informed design choices before you committed to the ever-growing arduous and increasingly expensive task of producing an ASIC. See Gary was a member of the ITRS and knew stuff about the future that we normal folks didn’t.
When Gary started talking about these ideas back in 1997, initially it was big big news and got a lot of play in EE Times. It was the subject of many industry panels and thus more EE Times articles. The thing was, however, that the EDA industry back then had a lot on its plate addressing a succession of must-solve-today big challenges—timing closure, Design for Manufacturing, leakage power management and so on. So while EDA vendors seemingly liked the vision (and a few brave vendors started on the problem right away), the efforts to develop ESL tools and Virtual Prototypes and the panels discussing them seemingly faded into the back pages, despite some vendors dressing like chickens to draw attention to the subject. Needless to say Richard and I wrote a lot of articles on the ESL and SVP over the next 10 years. After a while I was kicking myself for not writing a template. Still just about every year at DAC or any other EDA related conference there was at least one panel discussing the need for and viability of ESL tools and virtual prototyping technology with the few EDA vendors pioneering the space espousing that mass adoption of these flows was happening today. But the evidence to back up those claims was iffy, at best.
At some point in the mid 2000s it seemed that folks were likening Gary to the boy who cried wolf. The languages, tools and flows for ESL and the SVP were being developed and gaining some adoption but it was slow—it certainly wasn’t moving mainstream. For this and among other business changes in the EDA industry, Gary lost his big firm analyst gig.
Gary was bloodied but unbowed, persevered and stuck to his guns as independent analyst at garysmitheda.com.
Now as I write this, I have to say that Xilinx along with great help from our friends at Cadence are helping make ESL and the silicon virtual prototype a mainstream reality. Of the many cool new features of our newly released, built-from-scratch Vivado Design Suite is the AutoESL tool flow that will help Xilinx users begin their FPGAs at the C level if they wish. In addition, with the release of Zynq-7000 extensible processing platform (which recently won the UBM Ultimate SoC of 2011), we also announced the Silicon Virtual Prototype of Zynq-7000 from Cadence to help users quickly make system level architecture decisions about their design and decide what functions are best implemented in software programming of the ARM processor on the chip and what functions are best implemented in the programmable logic on the chip.
It would be a bit brash to state that these flows are going to change the world but with the extraordinarily large user base of the FPGA space, exponentially larger than the number of folks doing ASICs and ASSPs today, the flow holds great promise to finally becoming mainstream. Not only that it has the promise to allowing adventurous software designers to expand their horizons and program hardware too.
So the guy who cried “ESL and SVP” now gets to say “I told you so.” It may be just me but if there ever was someone who hasn’t received a Kaufman award but deserves one—it is Gary Smith…Goering deserves one too but that’s another story.
Editor's Note: If you are headed to Design Automation Conference in San Francisco this June, come see Gary’s opening “what’s hot at DAC” presentation on the show floor--Booth #310 at 9:15 a.m.
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