This entry is the first in the what to see at DAC blogs. It includes listing about the demos that companies will be showing in the area of verification...
Several weeks ago, I asked companies to send me information about the demos that would be showing at DAC this year. I am pleased to say that many companies responded. I hope you find this better than another list of what you must see at DAC, instead, you can be guided by some real information that may actually be helpful in planning your trip around the show floor. Companies that did not get information to me, feel free to add your information by placing a comment on this article.
Simulation on the Cloud: Unlimited Possibilities. Aldec has enabled running RTL and Timing simulation on the secured cloud, providing access to a virtually unlimited number of high performance servers.
OS-VVM Community. OS-VVM delivers verification test methodologies, including constrained and coverage-driven randomization, as well as functional coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.
UVM verification and Debugging. Riviera-PRO is a verification platform that delivers SystemVerilog design entry, simulation, debugging. Provides latest support for UVM 1.1a, enabling creation of reusable testbenches and interoperable Verification IPs.
Emulation. Learn how Aldec is able to run emulation at over 10MHz on a 100 Million gate ASIC design. Aldec’s mixed language RTL simulator connects to emulation solution providing an emulation environment with true RTL view of hardware debugging data. With the recent release of SCE-MI 2.1 behavioral compiler support you can convert System Verilog transactors with DPI-C function calls to synthesizable code that runs in the FPGA board allowing for the design to run at emulation speeds. In addition to that Aldec is presenting virtual modeling platform integration with HES emulator based on ARM Cortex-A9 and AXI4 interconnected design. Demo with Linux running on virtual platform is also available.
Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness.
SpyGlass CDC: This demo will show how to perform protocol-independent clock domain crossing analysis at the block as well as at the SoC level. They will also demo a power intent-aware clock domain crossing analysis.
Berkeley Design Automation
Berkeley Design Automation will be demonstrating the Analog FastSPICE (AFS) Platform. AFS is a nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits. AFS delivers foundry-certified nanometer SPICE accuracy. For circuit characterization, the AFS Platform includes silicon-accurate device noise analysis and delivers near-linear scaling with the number of cores. For large circuits, it delivers >10M-element capacity and co-simulation with leading Verilog simulators.
Booth # 2509
Blue Pearl Software Suite offers RTL analysis, CDC checks and automatic SDC generation for FPGA designs. Its Visualization Verification Environment and design technology give users feedback for validating automatically generated pre-synthesis longest paths and SDCs, to drive the efficiency of synthesis and place & route tool. DAC demos include showcasing these capabilities with the latest FPGA tools and flows in the FPGA ecosystem, including flows with Synopsys Synplify Pro and Xilinx Vivado.
Breker Verification Systems will be showing TrekSoC which solves functional verification challenges associated with complex SoC designs containing embedded processors by automating self-verifying C test case generation for multi-threaded SoCs.
Functional Verification – Methodology and Automation
Successful verification of today’s gigagate SoCs requires a mix of methodology served by high-performance automation. They are highlighting new work flows that address the pain points that consistently top their customer surveys: low power verification, advanced debugging, enabling formal analysis for all engineers, and automating planning & management to track progress and reach coverage closure in all domains (digital, firmware, AMS, and assertions/formal).
SLEC HLS - Reduce HLS verification with C to RTL formal equivalence checking. They will be demonstrating how easy it is to apply in ESL Hardware Implementation Flows from Cadence, Forte and Calypto. This demonstration will provide a complete overview of the methodology, and will show how SLEC provides concise counter examples to quickly and productively identify the source of any design differences.
SLEC RTL - RTL to RTL equivalence checking focused on verification of ARM hardening flows. They will be showing how you can verify sequential optimizations made to an existing RTL design. A major application for SLEC RTL is in ARM "hardening", where engineers are modifying the ARM RTL for lower power or increased performance. SLEC RTL gives the users a way to formally prove that the initial and modified RTL are functionally equivalent.
Carbon Design Systems will showcase 100% accurate ARM reference platforms from its IP Exchange web portal. The platforms support Carbon’s Swap 'n Play technology allowing an OS to boot in seconds while still being able to debug with 100% accuracy. Carbon will demonstrate performance analysis and firmware debug on a 100% accurate virtual prototype utilizing ARM’s big.LITTLE processing technology. The demo will highlight why using 100% accurate Carbon models is the only way to ensure that results match the silicon to avoid the risk of a re-spin.
Booth ARM CC #802, #517
CISC Semiconductor will be showing their toolset System Architect Designer, SyAD, which enables the creation of functional verification tests automatically from the specification. It is used especially in automotive. SyAD ties together different model levels and disciplines in a distributed simulation environment from Matlab to SystemC to digital to A&M-S & HW/SW co-simulation.
EVE - Packaged in a small footprint, the ZeBu family of hardware-assisted verification solutions combines multi-MHz execution speeds, scalable capacity that ranges from several million to more than one billion ASIC-equivalent gates and 100% design accessibility. EVE will demonstrate during DAC how ZeBu takes hardware/software co-verification to the next level, with its latest in hardware debugging and power-aware verification technology, and integration with system-level software and test environments.
Flexras Technologies (New exhibitor) will be showing timing-driven partitioning technology for both ASICs and FPGAs. The Wasga partitioning tools allow the development of high-performance applications in FPGA-based systems and provide engineers with an easy path to prototype next generation SoCs using multi-FPGA boards. Wasga consists of two pieces: the Wasga Compiler: Timing-driven partitioning tool for ASIC and SoC rapid prototyping using multiple FPGA boards, and Wasga Architect : Board synthesis tool for FPGA-based applications.
Booth # 2810
ICScape (New exhibitor) - Aeolus is a parallel analog simulator. With an architecture that uses an efficient memory footprint, Aeolus is capable of simulating designs with tens-of millions of elements at the accuracy level comparable to traditional SPICE. Aeolus is 10X faster than traditional SPICE simulators and gains additional speed up through multi-threading acceleration. Aeolus can be integrated with leading custom design platforms.
Jasper Design Automation
Jasper will be showing their recently announced JasperGold Apps products. JasperGold Apps help customers achieve productivity gains in design and verification through individual Apps within a shared interactive environment that fit into existing verification flows. The JasperGold Apps helps solve engineers’ toughest problems, addressing an array of design and verification functionality issues throughout the flow.
NextOp - BugScopeTM helps design and verification engineers uncover corner-case bugs, expose functional coverage holes, and increase verification observability by enhancing existing simulation, formal and emulation flows. BugScope leverages design and testbench information to automatically generate assertions and functional coverage properties for progressive and targeted verification of complex designs.
BugScope assertion synthesis takes an RTL design and testbench and automatically synthesizes:
High quality assertions, which capture key design specifications and constraints.
Functional coverage properties, which expose holes in the testbench and verification plan.
Booth # 900
Meridian CDC is a Clock Domain Crossing solution. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. Meridian CDC injects metastability and generates checkers to enable dynamic CDC verification using simulation. The demonstration of Meridian CDC will feature its ease-of-use, intuitive reporting and low-noise that virtually eliminates false errors.
Ascent Implied Intent Verification (IIV) is an early functional verification tool that helps finding elusive bugs in the RTL. Ascent IIV performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis. Ascent IIV can improve verification efficiency and detect up to 50% of design functional errors prior to testbench development and simulation. The demonstration of Ascent IIV will highlight how easy it makes formal analysis to quickly and automatically find design bugs.
Ascent XV. Xs in simulation can cause the masking of functional bugs (X-optimism) in RTL and unnecessary X’s (X-pessimism) in netlist, both of which result in differences between RTL and netlist simulations. Ascent X-Propagation Verification (XV) addresses both issues. Ascent XV provides a hazard report for assessing design susceptibility and an X-accurate model for X-verification in simulation. The demonstration of Ascent XV will demonstrate the ease of signing off on functionality in RTL and eliminating unnecessary Xs in netlist simulations.
Meridian Constraints is a constraint management solution. It offers constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities designed to provide users with ultimate confidence in the timing constraints employed across all phases of implementation flow. The demonstration of Meridian Constraints will show how easy it is to find holes and inconsistencies in SDC decks to ensure sign-off is complete and correct.
S2C has added 7 new Prototype Ready accessories to the already large family of daughter cards used to create FPGA-based prototypes and interface FPGA-based prototype boards to the user's target operating environment. These pre-engineered off-the-shelf solutions speed the overall prototype development schedule by saving the user the time to engineer the solutions on their own.
Tanner EDA HiPer Simulation A/MS: Tanner’s latest Analog/Mixed-Signal offering that bridges Analog and Digital Verification. They will be Verilog A and Verilog A/MS within T-Spice integrated with Aldec’s Riviera-PRO simulator.
Booth # 1126
SpringSoft will demonstrate its products that make it easier for engineers to do more functional verification in less time.
Verdi3 has introduced a new version of its debugger featuring user personalization, customization, and interoperability. Also new is a simplified GUI-enabled integration of custom applications created with the Verdi Interoperability Application (VIA) platform. This provides open access to the Verdi design knowledge architecture and software infrastructure to facilitate development of Open Source scripts/utilities tailored to user design flow and tool requirements.
Certitude Functional Qualification System applies mutation-based testing techniques with static analysis to measure verification effectiveness, identify significant weaknesses, and improve QoR of HDL simulation-based environments. Advanced fault detection and checker qualification innovations provide early feedback and refine results analysis, enabling broader and more efficient deployment of verification qualification methodologies throughout the SoC functional verification signoff flow.
ProtoLink Probe Visualizer used to increase design visibility and cut debug time in half for custom-designed and off-the-shelf FPGA prototype boards. Probe Visualizer enables users to probe large numbers of signals over many cycles, easily add/change signals with fast probe ECO flow, and debug designs at the register transfer level (RTL) with SpringSoft’s Verdi Automated Debug System.
Hybrid Prototyping - This demonstration will showcase an SoC design prototype distributed across Synopsys Virtualizer, a SystemC/TLM based virtual prototyping environment, and a Synopsys HAPS-64 system, an FPGA-based ASIC prototyping system.
Enabling Verification of Advanced SoCs - This exhibit includes what's new in VCS® including the latest innovation and technology in verification planning/management, simulation, testbench methodology, coverage, next-generation VIP, advanced debug, and leading low power verification. The demonstration will also highlight critical links for the System-to-Silicon (S2S) SoC verification, including how SoC leaders use VCS with virtual prototyping, FPGA prototyping, as well as analog/mixed-signal simulation to reach verification goals on schedule.
HiPer Simulation AFS: Tanner’s latest front-end Design & Simulation offering bolstered by BDA’s FastSPICE capability. They will be showing T-Spice and Berkeley Design Automation FastSPICE tools in action.
HiPer Simulation A/MS: Tanner’s latest Analog/Mixed-Signal offering that bridges Analog and Digital Verification. They will be Verilog A and Verilog A/MS within T-Spice integrated with Aldec’s Riviera-PRO simulator.
Booth # 1126
Clarus - Even with perfect RTL, validation of today’s SoCs is difficult and time consuming, particularly in complex designs where hardware, software, and firmware come together at first silicon. The Tektronix Clarus embedded instrumentation solution speeds debug and validation of these complex systems by adding on-chip logic analysis solution to the RTL. Clarus automates instrumentation of the device and uses advanced software to analyze the design at-speed. Clarus delivers comprehensive, real-time visibility into internal signals – with more visibility than is possible with ad-hoc approaches to instrumentation.
Certus ASIC Prototype Validation Solution. The Certus Debug Suite accelerates functional verification of ASIC prototypes. The debug suite is able to produce a single waveform view of a complete ASIC design during multi-FPGA prototyping and can zoom from a multi-second view down to the bit level. This, combined with the ability to select a wide range of signals without the need for continual FPGA re-synthesis, speeds debug analysis so that designers can quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move ASIC designs into production.
Vennsa - OnPoint™ is automated debugging software that localizes the source of errors with no user guidance. It eliminates time-consuming manual debugging of RTL failures that takes more than half of the verification effort. OnPoint automatically points engineers to the root cause of failures and suggests how to fix the bugs for faster design closure and improved productivity. Vennsa will demonstrate OnPoint and its new features in causality analysis, forward debugging and sub-system level debugging during DAC.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).