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Gearing Up for DAC – Verification demos

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re: Gearing Up for DAC – Verification demos
dunncarole5   5/30/2012 5:32:15 PM
Mentor Graphics - Verification continues to be the greatest bottleneck in the design cycle. Despite the plethora of verification tools, none have the depth or breadth to offer a complete measurable solution. The Questa Verification Platform uniquely provides a comprehensive solution that addresses the SOC verification explosion with a platform comprised of advanced verification methodologies, high performance simulation, intelligent testbench automation, software/hardware unified debug, formal, CDC, low power, analog-mixed signal, VIP, a central unified database and automated analysis tools, as well as integrated flows with ESL and emulation. Come visit the Mentor booth #1530 and Mentor’s Verification Academy booth #1514 to learn about the Questa Verification Platform, Questa’s leading edge support for UVM, as well as Questa’s comprehensive solutions targeting low power, and accelerated coverage closure, and new solutions for getting the most out of formal verification.

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re: Gearing Up for DAC – Verification demos
Deepak.Shankar   5/23/2012 11:38:01 PM
Name: Mirabilis Design Inc. Booth Number: 1906 Product Name: VisualSim Architect Description: VisualSim is the graphical modeling and simulation software for the rapid exploration of architectures to optimize the product specification for functionality, power and performance. Using the prebuilt modeling libraries in VisualSim, engineers can assemble models of their proposed system in a graphical editor. Users can then instantiate pre-defined analysis reports and conduct simulation studies over a wide-range of attribute values. Using the recommendations provided by the output reports, the designers can arrive at a system specification that is optimized to meet the customer performance requirements at the target price, weight, reliability and power constraints. VisualSim is used by Systems Engineers, Architects, Software Designers and Program Managers. What is new: 1. End-to-end system power generation, consumption and management. This is a new library and methodology that enables designers to explore different power sources, consumption and power conservation/management. The user can construct models containing mechanical, electrical and electronic components. The designer can experiment with different conservation, operating environment, fault conditions and measure the power consumed in each scenario. 2. Software Validation. An graphical environment with checkers and tests to evaluate the functional operation of a distributed software running on independent cores, processors and systems that collectively form an product. This takes fully debugged code and run it over a simulation model, to emulate a vehicle or industrial control or aircraft. The system checks for safety compliance such as ISO 26262, responsiveness to fault conditions and expected latency, bandwidth and power consumption.

EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
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