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Gearing Up for DAC – Above RTL

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re: Gearing Up for DAC – Above RTL
mdos   5/24/2012 8:58:06 AM
Name: CubedEDA technologies Product: C cubed compiler synthesis tool Description: The C-cubed compiler is based on formal techniques and transformations to automatically generate, provably-correct and synthesizable RTL models (both VHDL or Verilog), from high-level, abstract ADA algorithms. An ANSI-C front-end is also on the way... In this way, the whole system can be modeled in algorithmic ADA and be verified at this level. Due to formal methods used, no lengthy RTL simulations are required, which saves many man-months of RTL or gate-level verification time.

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re: Gearing Up for DAC – Above RTL
Deepak.Shankar   5/23/2012 11:37:22 PM
Name: Mirabilis Design Inc. Booth Number: 1906 Product Name: VisualSim Architect Description: VisualSim is the graphical modeling and simulation software for the rapid exploration of architectures to optimize the product specification for functionality, power and performance. Using the prebuilt modeling libraries in VisualSim, engineers can assemble models of their proposed system in a graphical editor. Users can then instantiate pre-defined analysis reports and conduct simulation studies over a wide-range of attribute values. Using the recommendations provided by the output reports, the designers can arrive at a system specification that is optimized to meet the customer performance requirements at the target price, weight, reliability and power constraints. VisualSim is used by Systems Engineers, Architects, Software Designers and Program Managers. What is new: 1. End-to-end system power generation, consumption and management. This is a new library and methodology that enables designers to explore different power sources, consumption and power conservation/management. The user can construct models containing mechanical, electrical and electronic components. The designer can experiment with different conservation, operating environment, fault conditions and measure the power consumed in each scenario. 2. Software Validation. An graphical environment with checkers and tests to evaluate the functional operation of a distributed software running on independent cores, processors and systems that collectively form an product. This takes fully debugged code and run it over a simulation model, to emulate a vehicle or industrial control or aircraft. The system checks for safety compliance such as ISO 26262, responsiveness to fault conditions and expected latency, bandwidth and power consumption.

EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
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