This entry is the third in the what to see at DAC blog series. It includes listing about the demos that companies will be showing in the area of RTL to GDS II
Several weeks ago, I asked companies to send me information about the demos that would be showing at DAC this year. I am pleased to say that many companies responded. I hope you find this better than another list of what you must see at DAC, instead, you can be guided by some real information that may actually be helpful in planning your trip around the show floor. Companies that did not get information to me, feel free to add your information by placing a comment on this article.
Previously published are Verification and Above RTL
RedHawk™-3DX, the fourth-generation power-sign-off solution from Apache Design extends previous generations’ capabilities to address sub-20nm designs with 3-GHz+ performance and billions of gates. It is architected to support the simulation of emerging chip and packaging technologies using multi-die 3D-ICs for smart electronic products. Apache’s DAC demo will introduce its new RedHawk™-3DX multi-tab, multi-pane GUI that enables greater flexibility and productivity for analyzing multi-die designs. It will demonstrate RedHawk-3DX’s ability to view voltage drop hotspots from multiple chips in a 3-D stack-up simultaneously, enabling designers to qualify input data, review overall design weaknesses and debug specific hotspots; leading to more robust IC designs.
Booth # 1813
At DAC, ATopTech will highlight their product Aprisa, a netlist to GDSII solution, including placement, MCMM clock tree synthesis, MCMM optimization, and router. At the core of the technology is Aprisa's hierarchical database. The solution includes RC extraction, design rule checking (DRC) engine, and a timing engine to solve the complex timing issues associated with variation (OCV, AOCV, and POCV), signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa also supports double patterning technology (DPT)-compliant placement and routing design rules as well as other 20nm design for manufacturing (DFM) rules.
SpyGlass Physical Base: This solution will demonstrate how designers can quickly identify and fix logical congestion problems during RTL development, avoiding design closure issues normally realized only after many iterations through physical implementation.
GenSys Assembly: Atrenta will demonstrate how to automate the assembly of your chip at the architectural level. They will also address the demanding requirements for RTL restructuring due to ECOs and architecture changes with an automated flow.
SpyGlass Physical Advanced: Atrenta is addressing how floorplanning at the early RTL stage can optimize your design architecture for convergence. They will demonstrate how to analyze and optimize critical timing paths, routing congestion and power; handing off an initial floorplan to the back-end that will ensure easier design closure.
SpyGlass Physical 2.5D: See their unique 3D RTL planning and optimization tool applied to 2.5D silicon interposer design challenges.
SpyGlass Physical 3D: See their unique 3D RTL planning and optimization tool applied to true stacked die memory on logic design challenges.
SpyGlass DFT: Atrenta will be talking about their RTL testability solution. See how to improve your stuck-at and at-speed coverage early in the process and insert BIST structures automatically at RTL.
SpyGlass Constraints: Atrenta's constraints management solution will show how to manage timing constraints and false/multi-cycle paths.
Their software suite offers RTL analysis, CDC checks and automatic SDC generation for FPGA designs. Its Visualization Verification Environment and design technology give users immediate feedback for validating automatically generated pre-synthesis longest paths and SDCs, to drive the efficiency of synthesis and place & route tool. The DAC demos will showcase these capabilities with the latest FPGA tools and flows in the FPGA ecosystem, including flows with Synopsys Synplify Pro and Xilinx Vivado.
PowerPro Platform – They will show how the Sequential Analysis Technology of PowerPro can enable you to achieve the lowest-power SoC design. This suite session demonstrates, RTL power optimization across an entire SoC, including automatic clock gating, memory gating and light sleep controller generation, provides upfront RTL power estimation using the built in logic synthesis engine, eliminate design risk with sequential formal verification and PowerPro's ECO flow.
Concept Engineering helps electronic design engineers to understand, debug, optimize and document electronic designs. Concept Engineering's debugging and visualization software StarVision, RTLvision, GateVision, SpiceVision and SGvision are customizable debugging tools for electronic design engineers. Our automatic schematic generation, navigation and viewing technology Nlview/ T-engine is available as software component/library for EDA tool developers. Our technology is used in many fields, including: RTL development, IP reuse, ASIC and SoC design, Analog mixed-signal design, synthesis, verification, post-layout analysis, System/RTL/netlist debugging and visualization.
ICScape (New exhibitor)
TimingExplorer is a Multi-Corner-Multi-Mode physically-aware timing ECO tool. TimingExplorer reduces timing ECO cycle by up to 50%. TimingExplorer can be easily integrated with existing physical implementation flows and signoff STA tools.
ICScape - ClockExplorer is a driver to complex SOC clock tree synthesis. It reduces clock tree synthesis iterations and improves quality of results (QOR), such as latency, on-chip variation (OCV), buffer level, buffer count and power. It fits into existing clock design flows, complementing current physical design and clock tree synthesis tools.
ICScape - Skipper has the capacity and performance to address SOC chip integration, chip finishing and tapeout. Advanced database compression and geometry processing technologies enable Skipper to use an efficient memory footprint, and with multi-threading acceleration, it significantly improves productivity for ultra-large layout processing. Skipper also provides many functions such as layout viewing, editing, rapid layout comparison, built-in DRC/LVS debugging, massive IP merge, SEM image processing, focused ion beam (FIB) and 3D layout views, etc. Skipper supports GDSII, OASIS and MEMBES.
ICScape is demoing (sign up required) an integrated native-OpenAccess based analog/mixed signal design platform. This includes schematic entry, schematic-driven-layout, custom layout design, the new digital block automatic placement & routing, together with physical verification, parasitic extraction and mixed signal verification.