This weekly posting provides a condensation of some of the best EDA and IP blogs from the web over the past week. If you have a blog feed that you would like me to consider, please let me know and I will include it in future editions.
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions – Richard Goering
Three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given the right tools and methodologies, and solutions are becoming available now.
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test – Richard Goering
Logic BIST tests the functional logic, but it did not get much traction except for some high-end CPU server and networking chips. Now, LBIST is back -- but generally not for manufacturing test, as you might expect.
Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition – Jason Andrews
Jason made two postings this week that between them cover the top six most frequently asked questions related to using the Xilinx Zynq-7000 Virtual Platform as a VirtualBox Appliance.
Three Tips from Sid Faulkner For Preparing To Sell Your Startup – Sean Murphy
Sean Murhy talks about a talk given by Sid Faulkner, CFO of Ciranova “Navigating the Treacherous Path of Mergers and Acquisitions”.
Turn off your phone! - Patrick Carrier
Everybody knows you are supposed to turn off your phone and other electronic devices when you are on a plane. I like to remind people in case they “forget”. I tend not to make a big deal during takeoff, but landing has me a little more on edge.
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!" – Axel Scherer
We have released a set of byte-size videos about the basics of the Universal Verification Methodology (UVM) for SystemVerilog. Each video is under 5 minutes long and includes sound, so put on your headphones.
Rooster Tail Engineering – Mike Jensen
What was cool and unusual yesterday is commonplace today. But even something that might become commonplace can remain extraordinary if we only see it once in a while. My recent weekend excursion is a perfect example…
Getting the Least Out of Your Verification Effort – JL Gray
It's quite common to read blog posts or industry newsletters giving you tips on how to succeed with your verification efforts. But all of these people are probably trying to sell you something. Don't let them do it! Follow these easy steps and you'll be amazed at how much less stressful your life becomes:
UVM Drivers and Monitors – JL Gray
I am frequently amazed to find that there are a large number of verification engineers who insist that creating a monitor is often not useful. These engineers prefer to perform checking based directly on the stimulus generated in a test, sequence, or driver.
Brian Bailey – keeping you covered
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