There is such a thing as a free lunch and here is your opportunity to get two in one month if you live in Silicon Valley. Find out about design data management and the challenges of DDR memories...
There are two great events coming up in February that I would like to bring to your attention. Both are free which makes them very affordable – only requiring your time and attention. The first is the Silicon Valley DVClub that will take place at Dave and Buster’s in Milpitas. Not only is it free but lunch is provided. The speaker will be Dean Drako, CEO and president of IC Manage.
Title: IP Reuse impact on Design Verification Management across the Enterprise
Designing hardware is becoming more like designing software in that it is increasingly a process of ‘continuous design’. To achieve continuous design, businesses are maximizing the reuse of IP modules across designs and design derivatives.
As such, companies must address the increasingly complex dependency management associated with the reuse of their IP blocks and subsystems, which evolve dynamically and incrementally as the IP is distributed and reused. Dependency management is needed for communication between IP developers, consumers, verification teams and management through the entire space of IP derivatives across the enterprise.
What is the most efficient process for ensuring design verification information flow and real-time sharing and access to this information? What information must be captured, encapsulated with the IP and shared - such as bug rollouts and propagation of fixes? What internal processes are needed to support such an infrastructure?
To register click here
The second event happens on February 7th at the Sana Clara TechMart Conference Center. This is a half day event that also includes lunch! The event is titled “Uniquify DDR with Confidence Technology Symposium” with an objective to:
- Summarize the current state of today's DDR technology and existing design practices
- Discuss specific challenges designers faced when implementing and deploying DDR-based designs
- Examine the impact of DDR design practices on device yield and system reliability
- Recommend best implementation practices for the entire DDR subsystem
- Introduce a state-of-the-art DDR solution that directly addresses the most pressing DDR challenges
You can register for this event here.
– keeping you covered
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