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What's Your Take on Tabula?

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ibiquity
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re: What's Your Take on Tabula?
ibiquity   3/2/2010 7:49:02 PM
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10 years ago there were reconfigurable FPGA's. Is there something fundamentally diffferent about these? I also question the phrase (spin?) "We don't ask customers to do anything fundamentally different than they've done before," Please define "Fundamentally Different". Just coding for configurabnility is fundamentally different.

mcgrathdylan
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re: What's Your Take on Tabula?
mcgrathdylan   3/2/2010 11:00:22 PM
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Not exactly an outpouring of reaction so far. But perhaps you are just warming up. I'd love to hear from some readers on this.

jg_
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re: What's Your Take on Tabula?
jg_   3/3/2010 2:33:39 AM
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There is plenty of spin, and 'patent dance' sounding talk, but the core idea seems to be 'multi threading' or time slice/serialize of the logic. That can save routing and LUTs but not save config memory and it will ADD the config-mux logic cost, between slice storage, and power impact. The real test will come down to the SW, and if it will do the 'slice and dice' needed on the code, and if that will be debug-able.

amiga89
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re: What's Your Take on Tabula?
amiga89   3/4/2010 3:01:30 PM
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There is not that much actual information available on the technology, but here goes. Assumption. The configuration information is set up in a circular shift register, so in effect n (8?) circuits running at less than clock divide by n Mhz can run as long as they don't need to interact. Think of it as hyperthreading for logic. From there it gets complicated. I worked on the same sort of thing used for simulation over 10 years ago, bottom line is designing for these devices is tough if you want to take advantage of the density multiplication. Given that FPGAs have a density disadvantage over ASICs of at least 20 to 1 anything that cuts that down to under 5 to 1 really moves the point when it is worthwhile to go to ASIC. Assume less than 2T (transistors) for each config bit you get to reuse the routing fabric and any hard logic for very low area cost. I am going to assume that the tools are going to be problematic in the beginning. The make or brake here will be the cost of the devices. If these devices are cheap enough so they can compete with ASIC and then the design wins will come. The path will become FPGA for prototype, Time Div Logic Arrays for medium production and ASIC only if there is absolutely no alternative or massive volume. If the cost advantage is great enough, the money available will quickly generate FPGA to TDLA conversion engineers and service bureaus who are willing to endure the pain of a new tool chain. BUT we do not know much about the IO, the power profile or the cost and historically configurable logic manufacturers have not been very good partners for high volume, preferring to get much of their profit from the high end. The game is afoot..

clematis
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re: What's Your Take on Tabula?
clematis   3/4/2010 3:16:07 PM
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I went to the Tabula website to learn more about the chips. It seems that if the chip performs as advertised it will be able to effectively operate in the 1 GHz range. However there is little detailed info for an engineer wishing to see the nitty gritty. They make you register to obtain any data - big mistake, they should be offering copious and easy downloads for their product info. I did register thinking I would quickly get a return email allowing me to access more info. I'm still waiting. The website seems geared toward investors, not engineers. If they want engineers to design in their chips they will have to become more engineer friendly. But the info I got about the chips seems really cool. John

clematis
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re: What's Your Take on Tabula?
clematis   3/4/2010 3:16:18 PM
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I went to the Tabula website to learn more about the chips. It seems that if the chip performs as advertised it will be able to effectively operate in the 1 GHz range. However there is little detailed info for an engineer wishing to see the nitty gritty. They make you register to obtain any data - big mistake, they should be offering copious and easy downloads for their product info. I did register thinking I would quickly get a return email allowing me to access more info. I'm still waiting. The website seems geared toward investors, not engineers. If they want engineers to design in their chips they will have to become more engineer friendly. But the info I got about the chips seems really cool. John

mcgrathdylan
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re: What's Your Take on Tabula?
mcgrathdylan   3/4/2010 3:35:30 PM
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Thanks for the great comments. These is the kind of detailed stuff we needed. Anyone else want to weigh in here? Clematis, I appreciate your effort to make this forum more active by submitting twice, but I'm afraid people will see right through that strategy. :)

clematis
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re: What's Your Take on Tabula?
clematis   3/4/2010 3:41:29 PM
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Ah, busted again! My browser seemed stuck when I hit "send" - so I hit it again. Glad I wasn't purchasing something!

pabitt
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re: What's Your Take on Tabula?
pabitt   3/4/2010 3:54:54 PM
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This technology does not lend itself to real time streaming communications. A modem per say or any networking device that has data constantly being streamed to it may not be able to halt the data and reconfigure for the next function without valuable data being dropped. If the processing was fast enough you could theoretically get through all of it in time before the next bit of data arriving at the physical port but to meet line rates of 10Gbps or greater I don't see this happening. Maybe for smaller more processing intense applications this technology has an advantage. Seems like more of a niche product than a general main stream technology. Not to mention that the giants (Xilinx & Altera) have been working on real time reconfiguration for a while. I would imagine if the bulk of the market were really interested in this technology that it would have been made a reality before now.

chinookpass
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re: What's Your Take on Tabula?
chinookpass   3/4/2010 4:07:32 PM
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Two main questions. Do area and power tradeoffs equal a win? What portion of standard designs map well into this structure? This does not appear to be real-time configuration that pabitt is talking about since it is on a per cell basis and it is cyclical in nature over 8 cycles.

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