In the stories of the Wild West from the 1800s, the image of a cattle drive often is depicted. A small team of cowboys deliver thousands of heads of cattle to market. The cowboys spend many days crossing open land until they reach their destination -- one with stock yards to accept their precious herd, and a rail station to deliver it quickly to market. Along the way there are dangers, including losses by predators and mad stampedes by cattle rushing blindly when frightened or disturbed. The primary job of the cowboys is to keep the herd on track and settled as they move to ship-out.
I see immediate parallels between the cowboys of the Wild West and today's system-on-chip (SoC) design and verification engineers. Cowhands struggle to control and move a big herd. Similarly, today's design teams grapple with how to keep a project on target and converging to tape-out, and successful when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track. How big are these new SoCs?
The Xbox One gaming console, for example, uses 5 billion transistors, which is equivalent to 1.25 billion digital gates. Its AMD-designed SoC produced at TSMC on a 28nm process combines eight Jaguar CPU cores and Graphics Core Next (GCN)-class integrated graphics. (See Figure 1.)
Figure 1. XBOX ONE is an example of a modern SoC with more than 1 billion digital gates.(Courtesy of Microsoft Inc.)
Another example, pictured on the left, is Nvidia's GK110 GPU (also made on TSMC's 28-nm process), which has 7.1 billion transistors. This translates to nearly 2 billion digital gates. These are not just big chips but giant chips!
With each smaller semiconductor node foundries provide, more gates can be squeezed into the same die size. In parallel, many different kinds of design blocks and intellectual property (IP) are employed, usually created by third-parties, to accelerate the implementation of the design objectives. The interaction of the various blocks across various power and timing conditions adds a new kind of complexity to the design. The result is a "herd" of interfaces with thousands of different crossings that must be checked and verified to ensure the design does not run off into a fatal operating condition.
It would be great to have the luxury of several hundred design and verification engineers to verify all possible failures in these giant SoCs, but that is not usually the case. Typically a small team relies on design automation software to manage the complexity of the verification challenge.
For each interface in the SoC, signals cross asynchronously between the various IPs and must be registered correctly to ensure the integrity of the digital signal path and eliminate metastability errors. For bus-level signals, circuitry such as a FIFO manages the data transfer and verification to ensure there is no data overflow or underflow that could compromise the design. This approach requires a full-chip clock domain crossing (CDC) analysis.
Design teams need three elements to achieve overnight CDC analysis runs for functional sign-off – precision, throughput and ease of use. (See Figure 2.)
Precise analysis means the software must accurately capture all possible interfaces in the design, including buses; provide reset analysis, including glitches in both asynchronous and synchronous domains; and correctly handle crossings that may be blocked by environment definition. Once the analysis is done, it is essential to be able to verify the interfaces automatically, using formal technologies, so all possible failure conditions can be exhaustively covered.