I may be the engineer in the family, but my wife is the inventor.

Being an engineer is easy. You go to school to learn well established laws and methods. When you get a job, there are others who can mentor you and show you the ropes. If you need to know more, there are training classes to take. Someone else, usually marketing, decides what needs to be to be designed. All you have to do is follow the rules.

Being an inventor is hard. There is no school for inventing, nobody to teach you the ropes, and no classes to tell you how to do things. You come up with your own idea that has never been done before. You learn on the fly what you need to know from a variety of domains you know nothing about. You build it yourself. There is no such thing as first pass success. Experimentation and refinement are a constant process.

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I was contacted a few weeks ago by Synopsys’ PR agency to see if I’d be interested in covering an upcoming product announcement. I usually ignore these "opportunities" since the information provided is usually carefully wordsmithed marketing gobbledygook and not enough for me to really form an opinion. However, it turned out that this announcement was on a subject I know a little bit about, so I took them up on their offer.

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http://theASICguy.com

I came across a tweet the other night that pointed me to a discussion on the EE Times forum regarding an editorial by Mark LaPedus a few weeks ago. The editorial states that “IBM Corp. has cut nearly 10,000 jobs this year, according to reports, although Big”. On the positive side there is good talent, though young and inexperienced, after some training support and management care they can contribute meaningfully on core projects, on the negative side the high turnover rate reduced the efficiency.

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It was easy to spot the big theme’s at DAC this year. This was the "Year of ESL" (again). The state of the economy and the future of EDA was a constant backdrop. Analog design was finally more than just Cadence Virtuoso. And social media challenged traditional media.

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Sean Murphy has the best one sentence description of DAC that I have ever read:

The emotional ambience at DAC is what you get when you pour the excitement of a high school science fair, the sense of the recurring wheel of life from the movie Groundhog Day, and the auld lang syne of a high school re-union, and hit frappe.

That perfectly describes my visit with Oasys Design Systems at DAC.

To read the rest of this entry, please visit Harry's blog here:
http://theASICguy.com

Last year, at the Design Automation Conference, there were only a couple dozen individuals who would have merited the title of EDA blogger. Of those, perhaps a dozen or so wrote regularly and had any appreciable audience. In order to nurture this fledgling group, JL Gray (with the help of John Ford, Sean Murphy, and yours truly) scrounged a free room after-hours in the back corner of the Anaheim Convention Center in which to hold the first ever EDA Bloggers Birds-of-a-Feather session. At this event, attended by both bloggers and traditional journalists, as John Ford put it, us bloggers got our collective butts sniffed by the top dog journalists.

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I’m writing to you today from a Coffee Bean & Tea Leaf in beautiful Southern California. There’s something about the atmosphere at a coffee shop that helps me get my thoughts together. Maybe it’s the white noise of the cappuccino machines or the conversations or music in the background.

I’m not the only one of course. Daniel Nenni and his two great danes can often be found at the downtown Danville Starbucks. And like the show Cheers, there are regulars at my local coffee shop that I see most days I am here. Sales people and college students come here a lot. And there has been a noticeable increase in another group. People out of work or “in transition”. In fact, as I glance over to the next table, I see a woman working on her resume. No lie.

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That’s the question that everyone was asking last week when Oasys Design Systems came out of stealth mode with a “chip synthesis” tool they claim leaves Synopsys’ Design Compiler and other synthesis tools in the dust. According to Sanjiv Kaul, Chairman of Oasys and former VP of Synopsys’ Implementation Business Unit, RealTime Designer can synthesize full chips up to 100 million gates in a single run, and do so 20x faster with smaller memory requirements and achieving better quality of results. Oh, and it also produces a legalized cell placement that can be taken forward into detailed routing.

To read the rest of this entry, please visit Harry's blog here:
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Guest bloog gy Narendra (Nari) Shenoy, Technical Program Co-Chair, 46th DAC.

Each year, around this time, the electronic design industry and academia meticulously prepare to showcase the latest research and technologies at the Design Automation Conference. For the casual attendee, after a few years the difference between the conferences of years past begins to dim. If you are one of them, allow me to dispel this notion and invite you to look at what is different this year.

To read the rest of this entry, please visit Harry's blog here:
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A few weeks ago I was talking with a former colleague about social media (or new media or web 2.0 or social networking or whatever you call it). He is now VP of sales at one of the companies in our industry and is contemplating starting a blog or doing something in social media and he wanted to get my thoughts. Early in the conversation, he asked ''do executives really read blogs''?

To read the rest of this entry, please visit Harry's blog here:
http://theASICguy.com