Tough questions for EDA execs John Cooley has been soliciting "edgy" questions for the annual EDA "bigwigs" panel at the Design and Verification Conference (DVCon). Some come with a clear message: stop the infighting over standards and languages.	Richard Goering EDA Software Editor
The panel, renamed this year as the "Troublemaker's Panel," will be held in San Jose, Calif. Thursday, Feb. 22, at 3:30 pm. Panelists include Rajeev Madhavan (Magma), Antun Domic (Synopsys), Joe Sawicki (Mentor Graphics), Ted Vucurevich (Cadence), Vic Kulkarni (Sequence), Atul Sharan (Clear Shape), Brett Cline (Forte), and Gary Smith (Gary Smith EDA). A long list of "edgy questions" for each of these panelists appears in the latest E-Mail Synopsys Users Group (ESNUG 462) posting. Engineers are wondering such things as: If its tools are so great, why doesn't Magma have more market share? What are the possible outcomes of the Magma-Synopsys litigation? How is Synopsys going to respond to the Cadence ETS (Encounter Timing System) threat to PrimeTime's monopoly? When is Mentor Graphics going to buy Magma or Sierra Design Automation to get into place and route? Why is Sequence's Vic Kulkarni pushing outsourcing in India? Why hasn't Clear Shape been acquired, and can it survive as an independent company? Why won't Forte take the "Bluespec design challenge?" Some of the most interesting questions, though, point to user disgust over the way Cadence and Synopsys are fighting over standards, including Cadence's Common Power Format (CPF) versus Accellera's Unified Power Format (UPF), and the Cadence-backed ECSM versus the Synopsys CCS current-source modeling formats. "Why must the industry waste so much resource on defining 'proprietary standards?'" asked one questioner. "The big EDA companies, i.e., CDN and SNPS, are wasting their resources and holding back the industry with silly battles over ECSM vs. CCS and CPF vs. UPF. No wonder growth prospects aren't enough to excite Wall Street — we keep reinventing building blocks rather than innovating." "It's VERY annoying to be forced to support 2 formats (ECSM from Cadence and CCS from Synopsys)," said another. And this question came in for Synopsys: "Why do you think that you get a hall pass for not truly opening up .lib and .sdc?" SystemVerilog support is an issue, too. "We use a Cadence NC-Sim/Specman combo with Synopsys Design Compiler for synthesis," wrote one respondent. "What we forgot was their System Verilog interoperability; they do not support the same subset of the standard!" But the standards question I'd most like to see raised is one I've never been able to get Cadence to answer: Are you going to open the Skill language, and if so when, and if not why not? One of the "edgy questions" for Cadence CTO Ted Vucurevich raised that point: "Is Cadence regretting opening up their database to competitors, or is it going to go the whole hog and open up Skill and Pcells, without which Open Access is useless in the custom and analog design space (unless you use Cadence)?" At least one reporter will be listening with interest for an answer. Posted by Richard Goering on Feb 15, 2007 04:41 PM in EDA Software

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