What you missed at DATE Okay, I wasn't at the Design Automation and Test Europe (DATE) conference this week in Nice, France, either. But here are a few of the news reports that caught my eye.	Richard Goering EDA Software Editor
First, a couple of new companies came to light — or at least, new to me. One is German company Computer Simulation Technology (CST), which is attempting to bring its microwave/RF 3D simulation tools into the wireless IC design flow. The company has a 3D electromagnetic simulator that lets designers examine signal and power integrity. Also, French EDA startup Satin IP Technologies introduced a "design-for-reuse software cockpit." The solution runs on a web server application and captures parameters affecting IP quality from multiple sources throughout the IP design and integration lifecycle. Although Synplicity left the ASIC synthesis market last year, the company is targeting ASIC designers once again with a new edition of its Synplify DSP product. This time, it's an electronic system level (ESL) design pitch. There are a number of competing solutions, so it will be interesting to see if Synplicity gains a foothold in the DSP ASIC market. Mentor Graphics rolled out its new Veloce accelerator and emulator at DATE. Its "emulation on a chip" architecture claims some impressive speed and capacity gains over Mentor's previous emulators. What Mentor seems proudest of its "transaction-based acceleration," also described as "virtual emulation." It helps raise hardware-assisted verification to a higher level of abstraction. If Mentor can't decide which term to use, it's a good indication of technology that crosses the line between traditional acceleration and emulation. A panel discussion on mixed-signal design revealed that the productivity of analog designers is quite low. With 65 nm technologies coming on strong, speakers called for a new breed of analog designers who can face the power dissipation constraints, increased leakage, device variability and model accuracy challenges that will come with 65 nm. Another DATE panel looked at the "divide" between programmable logic and systems-on-chip (SoCs). While there are a few exceptions, panelists noted that not many SoCs contain programmable logic, with FPGAs and SoCs largely an either-or choice. For these stories and many others from DATE, see the DATE conference page at our EE Times Europe web site. Meanwhile, for an engineer's view of DATE, check out the blog of verification engineer J.L. Gray. You can read about everything from Gray's flight delays en route to Nice to the keynotes, panels, and product announcements that caught Gray's attention. It's all part of an ongoing independent blog in which Gray shares his perspectives on IC verification. Posted by Richard Goering on Apr 20, 2007 08:13 PM in EDA Software

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