Did TSMC delay high-k--again? As reported, TSMC is struggling to ramp up its 40-nm process, due to yield issues. Now, TSMC appears to have delayed its high-k/metal-gate technology. Originally, TSMC's high-k/metal-gate offering was slated for the first quarter of 2010, according to the firm. That technology is slated for its 28-nm node. That article can be read here.	Mark LaPedus Semiconductor Editor
In a conference call this week, TSMC Chairman Morris Chang said that the company would ''tape-out'' 28-nm with high-k/metal-gate in ''late 2010'' or ''early 2011.'' Chang said that TSMC is engaged with 10 customers with its high-k. For some time, there has been chatter that TSMC will ship its 28-nm process--without high-k--in the first part of 2010. So in that regard, TSMC's 28-nm offering is not late. However, TSMC's high-k is late to the party. In comparison, IBM's ''fab club'' hopes to ship high-k by the end of 2009. This appears to confirm my suspicions that TSMC is struggling with high-k. ''TSMC has also not really mastered the art of 'high-k/metal gate fabrication,' '' said C.J. Muse, an analyst with Barclays Capital, in a recent report. ''After delaying its implementation to 28-nm, TSMC is hedging its bets with a traditional oxynitride gate also available at 28-nm. If, as suggested in trade publications such as those mentioned herein, the yield problem at 40-nm is due to leakage, then, at 28-nm, an oxynitride gate will expend even more power than a 40-nm chip, due to high severity leakage problems,'' he said. ''For gate engineering, Intel (mainly) and AMD, for years, had used KLA-Tencor’s Quantox and had not taken the development of high-k/metal gate architecture lightly. Now is the time that foundries are waking up to the seriousness of the engineering challenges below 40-nm.'' KLA-Tencor's Quantox XP offers a gate monitoring solution for today's advanced gate dielectric processes. Its ''ACTIV technology enables independent non-contact electrical test measurements of gate capacitance and leakage for in-line electrical process control,'' according to KLA-Tencor. My theory: TSMC was working on its own high-k. It didn't work. Then, it had to resort to ''Plan B.'' In April, ASMI announced that an undisclosed Taiwanese foundry has selected ASMI's Pulsar atomic layer deposition (ALD) tool for the volume manufacturing of its 28-nm node high-k gate dielectric process. Some speculated that the customer could be TSMC. In any case, ASMI's Pulsar was the first tool to be used in volume manufacturing of high-k gates, starting at the 45-nm node. ASMI's main high-k tool customer is Intel Corp. Another wild theory: Intel recently licensed its Atom IP to TSMC. Intel and TSMC denied the deal involved high-k. Now, I'm really beginning to wonder if high-k is part of that deal. Posted by Mark LaPedus on Aug 1, 2009 11:46 AM in Semiconductors

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