Posted: 9/7/98

Capitalizing on what many term its "Core Store" business model, Mentor Graphics Corp. (Wilsonville, Ore.) has licensed its Virtual Library of soft cores to Siemens Semiconductor to support that company's Core Based Design (CBD) methodology and Semicustom Highway Design Environment. Under terms of the multi-year, multimillion-dollar agreement, Siemens customers will have access to a library that currently contains around 75 cores, said Bernd Braune, senior vice president at Mentor.

Braune said the agreement also names Mentor Graphics as a preferred provider of cores for Siemens. This means, according to Braune, that if Siemens or its customers require a core that is not found in the Virtual Library, Mentor will obtain the core and will honor it under the contract between the two companies. According to Siemens, the agreement will help it quickly adopt the CBD methodology before time-to-market pressure becomes too critical.

Mentor's Virtual Library includes numerous general-function cores such as microcontrollers, microprocessors, ISDN building blocks, peripheral controllers, DSP functions, QAM/QPSK and FEC codecs.

Sand Microelectronics (San Jose, Calif.) has announced a joint agreement with the Virtual Socket Interface (VSI) alliance to develop, pro bono, a modeling environment that facilitates the mix and match of cores that use on-chip buses.

Robert Nalesnik, vice president of marketing at Sand, said the company will provide a comprehensive test environment to validate core interoperability. Specifically, Sand will develop a standard virtual component interface (VCI) model that simulates how an intellectual-property core will operate both standalone and across a bus. Sand will also provide software to facilitate debugging and compliance verification with the VCI standard.

The company is taking on the project as part of a VSI pilot program to validate industry specifications before they are placed in the public domain. Nalesnik said Sand expects its VCI modeling environment and specification, which it is creating in Verilog, to be delivered to members of VSI's On-Chip Bus development working group in December.

Nokia is creating a VHDL version of the VCI modeling environment and specification and is expected to release it to the working group in the same time frame.

Argonaut RISC Cores (ARC; London) hopes that its ARC Partners Program will help it build alliances with partners developing intellectual property in key vertical markets with its synthesizable RISC microprocessor core. Bob Terwilliger, president and chief executive of ARC, said the first partner is Palmchip Corp. (San Jose, Calif.), which will use the core for its CoreFrame on-chip architecture.

Terwilliger said the Palmchip scheme will allow customers to mix and match other cores with the ARC processor to create system-on-a-chip devices, targeting such embedded applications in the handheld, multimedia, communications and consumer products areas. ARC hopes to develop links with partners in foundries, engineering services, RTOS, software and EDA tools,and to establish partnerships with such ASIC vendors as Fujitsu.

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