Posted: 10/12/98

EDA vendors Synopsys Inc. and Denali Software Inc. have separately announced model-generation offerings that support the Rambus Direct RDRAM spec.

Synopsys has incorporated the Rambus specification into its Logic Modeling MemPro memory-model generator. Denali announced that its MemoryModeler tool now supports Direct RDRAM, and that it is offering customers an additional RDRAM verification kit for more upfront functional verification.

Synopsys said its MemPro will allow designers to automatically generate multiple simulation-model configurations of the high-performance Direct RDRAM for functional verification of high-bandwidth memory systems. MemPro creates optimized memory models for ASIC, board and embedded-system design verification. It leverages Synopsys' Logic Modeling technology and support to ensure interoperability with other Logic Modeling hardware and software models and straightforward integration with Synopsys verification flows.

MemPro is available in several different packages starting at $5,950.

The Denali Direct RDRAM verification kit includes simulation models and performance-modeling and debug software. Designers can use the kit with Denali's MemoryModeler to create RDRAM models for controller and system design and verification.

The kit includes simulation models for Rambus ASIC Cells (RAC) as well as Direct Rambus RDRAMs; performance modeling based on Denali's recently announced AutoTest; and a customized RDRAM debugger. The RAC is a library macrocell used in ASIC designs to interface the core logic of an ASIC to the Direct Rambus Channel. It starts at $15,000 and includes support for VHDL and Verilog.

New Altera Megafunction Partner Program member Wipro Corp. has developed an optimized Inverse Multiplexing for ATM (IMA) controller core for use in Altera Corp.'s Flex 10K programmable-logic devices. The IMA core targets systems implementing the ATM Forum's inverse multiplexing for asynchronous transfer mode over multiple T1/E1 carrier links.

The core, optimized to fit into 4,200 logic cells on 10K100A or larger PLDs, features bidirectional IMA data-cell rate support; flexible bandwidth, from T1/E1 up to 8x T1/E1; common and independent transmit-clock modes; multigroup configuration; and support for all IMA frame lengths. It interfaces with ATM-layer and physical-layer devices in accordance with the ATM Forum's Utopia Level II, version 1.0. The IMA core controls the distribution of cells onto the group of links made available to the IMA. In the receive direction, it recombines the cells into the original data stream and presents the cell stream to the ATM layer. The core also performs differential delay compensation and frame synchronization for the incoming cell stream on a per-link basis. Configuration of the IMA megafunction is handled by an external microcontroller.

The IMA solution includes multiple licensable components. Licensing starts at $40,000.

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