Posted: 10/26/98

LSI Logic Corp. (Milpitas, Calif.) will unveil Fibre Channel cores this week aimed at devices on a local-area network, including disk drives, servers and switches.

Previous Fibre Channel cores-such as the Merlin family offered by LSI-ran into trouble with the disparate requirements of these devices. Disk drives sacrifice performance for price, while servers, for example, do just the opposite.

To get around this, LSI has adopted a modular approach to Fibre Channel cores. With the Merlin 2 family being released this week, LSI split off the basic requirements for Fibre Channel and put them into unmodifiable cores. These are added to customer-modifiable "bolt-on" cores to create controllers for different devices.

The central Fibre Channel core-which is also sold on its own-is the Merlin 2LPC. It acts as the arbitrated loop controller, the part that recognizes the Fibre Channel protocol and determines whether data is intended for its port.

The other unmodifiable core is the Fibre Channel engine (FCE), which handles the next level of sophistication: checking for errors and determining where to send data. Both are basic functions of any Fibre Channel switch

LSI's controller cores-the 2SL and 2DL-consist of the 2LPC, the FCE and an appropriately modified "bolt-on" core. The 2SL core is a basic combination of these three elements, while the 2DL core was created as a dual-port controller, often built into disk drives for redundancy and a popular option because it increases bandwidth. It adds a second 2LPC core to the 2SL design as well as a loop multiplexer to connect the 2LPCs to the Fibre Channel Engine.

Future generations won't need the multiplexer, using two 2SL cores instead, Tom Harrington, director of storage components at LSI, said. That won't be practical until costs fall further, so the 2DL is being offered as a stopgap.

This example is important, Harrington said, because it displays how the Merlin cores can save space and money. Normally, a dual-port disk drive has to incorporate two PCI-to-Fibre Channel boards, which now can be replaced by the lone 2DL core, he said.

Adding to the core startups, Sandcraft Inc. introduced its first general-availability core at the Embedded Processor Forum Oct. 15. Sandcraft's three founders developed MIPS' VR4300, the chip that won the Nintendo 64 contract.

The company was self-funded thanks to its first job, a MIPS processor core, commissioned by (and licensed to) NEC for the VR5400 processor used in inkjet and laser printers. With that design in hand, Sandcraft unveiled its first core for the general market. The SR1 is a hard ASIC macro based again on the MIPS architecture. The core takes advantage of out-of-order execution, using six execution units-including two integer units and a separate floating-point unit-to tackle instructions in parallel. The decoupling of the integer and floating-point unit also helps performance if a calculation stalls.

The SR1 is doing initial tape-outs at 0.18 micron and will be available in processes from 0.25 micron to 0.15 micron, said Dirk Smits, executive vice president of marketing. Its successors will be fragmented along three lines: high-performance cores, highýintegration (i.e. very small) cores and versions tailored to specific features.

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