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Posted: April 27, 1998
Quickturn's Affinity grows; Virage compilers see silicon
Core provider Integrated Intellectual Property Inc. and tool maker Quickturn Design Systems Inc. (San Jose, Calif.) will announce a strategic and technology marketing partnership this week. Integrated Intellectual Property will join Quickturn's Affinity Partnership Program and will integrate its standards-based I/O cores with Quickturn's design-verification products.
In the Affinity program, Quickturn works with core partners to develop models and methodologies that enable designers to verify system-on-chip designs using Quickturn's emulation and simulation tools.
According to the companies, Quickturn and Integrated Intellectual Property will work together to ensure their mutual customers receive the proper internal IP-block visibility and debug flexibility to get designs to market quickly.
Integrated Intellectual Property provides synthesizable, register-transfer-level (RTL) HDL cores for I/O and interconnect functions based on industry standards. It also provides integration and verification services.
The company joins ARM Ltd., Phoenix Technologies, Sand Microelectronics and SICAN Microelectronics in the core segment of Quickturn's Affinity program.
Virage Logic Corp.'s Custom-Touch and Self-Testable Memory Compilers will be available for the advanced 0.25-micron CMOS process at Chartered Semiconductor Manufacturing (Singapore) this month, with foundry tape-outs scheduled for later in the year. Virage (Milpitas, Calif.) also announced that it has released compilers that are silicon qualified at 500 MHz for Chartered's 0.35-micron process.
According to Virage, Chartered is the first foundry to support Virage's 0.25-micron memory compiler. Chartered's foundry customers using the Custom-Touch memory compilers will be able to embed optimized memory components into system-on-chip ICs without needing specialized memory-design expertise, Virage said.
The company claims that in a 0.25-micron CMOS process, the memory compilers can generate cells capable of supporting 700-MHz cycle times while consuming only one-fifth the power of previous designs. With the new compilers, designers can build cells that consume as little as 0.1 mW/MHz at 1.8 V without any significant area penalty.
Packet Engines Inc.'s Intellectual Property Group (Spokane, Wash.) has licensed its PE-ANEG Auto-Negotiation Module to Atmel Corp. (San Jose), which will provide it to ASIC customers for system-level integration.
In addition, the companies announced that Atmel will introduce an Ethernet 10/100-Mbit/s physical-layer transceiver (PHY) based on Atmel's analog technology and Packet Engines' PE-ANEG core.
The Packet Engines module is a full implementation of the auto-negotiation function defined in the 100 Base T Ethernet standard (IEEE 802.3u), and provides features for physical-layer transmission devices.
Edited by Michael Santarini.
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