Competitive ranks swell for IP model-compilation tools

The market for intellectual-property model-compilation and -delivery tools will become more competitive this week when Escalade Corp. and Summit Design separately announce products that target IP creators. Synopsys Inc., meanwhile, will up the ante in the IP tool space with plans to offer its IPx model-compilation and -exchange technology free with its Verilog and VHDL simulators.

The Escalade and Summit entries boast VHDL and Verilog model creation and strive to pull market share away from Synopsys' Verilog Model Compiler (VMC), which currently generates Verilog models only.

Escalade's new IP Guard uses proprietary compilation technology to create protected VHDL as well as Verilog models.

IP creators can use Escalade's DesignBook tool to aggregate descriptions in VHDL, Verilog, C, SDF and graphics from DesignBook and generate a generic representation. IP Guard takes that generic representation and performs analysis and optimization. Using technology originally developed by core vendor Advanced RISC Machines Ltd., the tool then creates a model targeted for a VHDL or Verilog simulator of the user's choice. IP creators can embed timing diagnostics into the protected model and can also embed multiple types of timing checks.

The tool starts at $228,000 and runs on Windows and Unix. It comes bundled with three copies of DesignBook and 40 hours of consulting time. Verilog simulators supported include Synopsys VCS, Cadence's Verilog-XL and Model Technology's ModelSim. VHDL simulators supported include MTI's ModelSim, Synopsys' VSS, Ikos and Cadence's Leapfrog.

Summit's new offering, Visual IP (VIP), includes the IP Model Compiler and the IP Model Manager. IP creators can use the Model Manager to create a VIP model. The IP Model Compiler allows core developers to create a single source model of their core in either VHDL or Verilog. The product then compiles the core and related design, verification and documentation data into a protected model.

The VIP model provides such design information as timing diagrams, input/output signals, access to selected internal registers, SDF timing shell, test vectors and user documentation.

The Model Manager's control panel allows the IP creators to set and remove breakpoints, override internal register values and specify input vectors. It includes an object browser and comes with a TCL/TK tool kit.

Visual IP runs on Unix and Windows platforms and starts at $100,000. Initial simulators supported include Model Technology's ModelSim, Cadence's Leapfrog and Verilog-XL, and Synopsys' VCS and VSS.

Synopsys, meanwhile, will offer a free, Synopsys-simulator-specific version of its VMC technology as a standard feature in its VCS Verilog simulator. The Verilog offering will be available in July, with versions for Synopsys' VSS and Cyclone VHDL simulators slated to ship in the fourth quarter.

Company officials said the feature, called IPx model compilation and exchange, is targeted at Synopsys-simulator users who want to create and exchange models but still protect them from tampering. If users want to export the models to tools from a third-party simulation vendor, they will need the VMC tool, which supports 30+ simulators.