Targeting semiconductor manufacturers that have 0.18-micron processes, Artisan Components Inc. (Sunnyvale, Calif.) this week will announce its HS500 family of SRAM embedded-memory generators for 0.18-micron (drawn) process technologies. The company said it can generate static random-access memories running at system speeds of more than 500 MHz in the worst case and, typically, at 850 MHz.

Artisan said the HS500 single- and dual-port synchronous SRAMs are targeted for high-performance applications, such as graphics, high-end computing and networking, and take full advantage of the latest 0.18-micron process technologies.

The company said the memory generators enable users to build as many memory instances with different configurations as needed, significantly reducing design time.

The HS500 family features Universal Test Interface support, which is included on all generated memories. The Universal Test Interface supports all standard test methodologies, including BIST, scan test, serial test and multiplexer isolation.

The company said that like its other generator offerings, the new HS500 family is "process-perfect"-tuned both electrically and geometrically to each customer's unique semiconductor process.

The Artisan HS500 family of embedded memory generators is available immediately. Pricing begins at $475,000 each for either single- or dual-port SRAMs, including all process tunings.

Altera Corp. (San Jose, Calif.) and a member of its Altera Megafunction Partners Program, Eureka Technology Inc. (Palo Alto, Calif.), have jointly announced the availability of Eureka's EC-240, a 64-bit PCI master/target core, which has been optimized for Altera's Flex 10K and Flex 6000 families of programmable logic devices (PLDs).

The EC-240 was recently implemented on an Altera EPF10K30A device, the companies said. The core was designed in synthesizable HDL and required 950 logic cells and zero embedded-array blocks in the Altera part. The core operated at 33 MHz and sustained burst transfers up to 266 Mbytes/second.

The EC-240 is designed to interface between the PCI bus and any user-configurable back-end device. It's said to operate as a bidirectional PCI-bus interface and performs all the data transfers necessary for the user-defined back-end device to access PCI memory or I/O.

A bus-mastering device, such as a video coprocessor or a DMA controller, initiates PCI access via the back-end interface of the EC-240. Supporting this environment, the core comes with a set of back-end design templates in either Altera Hardware Description Language (AHDL) or VHDL.

The core is available for evaluation via Altera's OpenCore capability, at no charge, through Eureka Technology's home page, www.eurekatech.com. Pricing for an encrypted net-list begins at $11,750. Eureka also offers a constraint file for timing and fitting, a simulation file and an installation guide.

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