Packet Engines' Intellectual Property Group has announced the next-generation design of its 10/100-Mbit/second Media Access Controller (MAC) core and the availability of other cores, including optional PHY interfaces for the MAC and complementary host-interface products.

The company said this next-generation product line was designed to meet the market demand for dependable, easy-to-implement cores, offered as modular blocks.

The new-generation MAC core, the PE-MACMII, replaces the Packet Engine's PE-MAC110. The company said while the major components of the MAC core remain unchanged, the PE-MACMII module offers a reduced gate count, ease of SCAN implementation, a single host register block for reconfiguration convenience and Media Independent Interface (MII) as the standard interface.

The PE-MACMII module is a dual-speed 10/100-Mbit/s Ethernet media access controller. It is compliant with IEEE 802.3u and 802.3x standards, supports CSMA/CD full and half-duplex modes, and has flow control. The company said it is optimized for switching and multiport applications, and may be interfaced to various buses.

The company also introduced additional interface cores, including the the PE-ENDEC core, the PE-PMD core and the Reduced Media Independent Interface PE-RMII core.

The PE-ENDEC core, which supports a 10T interface, is used to convert parallel data into 10-Mbit/s Ethernet bit streams that are supplied to a Manchester Encoded module for transmission on the LAN. The process can be reversed for receiving data.

The PE-RMII core is a 100-Mbit/s Ethernet PHY interface that only requires 6 pins, as opposed to the 16 required for MII, and the new PE-PMD module is targeted for use in 100X implementations.

Along with the new MAC and PHY interface cores, Packet Engines also introduced two complementary products: the PE-PCI2S and the PE-CDIF cores.

The PE-PCI2S core is a PCI-to-SBus core used for integrating PCI standard architecture into an SBus platform. The PE-CDIF core is a general-purpose clock-domain interface module designed to connect the 8-bit PE-MACMII core to a 32-bit external host.

The company also said it is offering the cores to semiconductor companies that wish to provide the cores as part of their ASIC library services. For a placement fee, the company said, ASIC providers can make all Packet Engines cores, including the Gigabit Ethernet line, available to customers.

VLSI Technology Inc. and Wipro Ltd. have disclosed an agreement to develop 1394 solutions for the custom IC market. VLSI has licensed rights to use Wipro's 1394 soft cores in its libraries of on-chip cores and building blocks.

The companies said that the agreement follows years of joint development between the companies on reusable 1394 cores.

The companies said the productized PHY and LINK cores will allow both to rapidly deploy high-speed serial communications functionality for consumer, communications and computer-networking applications.

Free Subscription to EE Times First Name Last Name Company Name Title Email address   Click here for your Free Subscription to EETimes Europe