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 Posted: July 20, 1998 Virtual Silicon joins hands with Amkor and NECLibrary vendor Virtual Silicon Technology Inc. (Sunnyvale, Calif.) has entered into a marketing and technology agreement with silicon and packaging vendor Amkor Technology Inc. (Chandler, Ariz.). The company also announced a library-development partnership with NEC Corp. The company announced it will support Amkor's second-generation 0.25-micron semiconductor process with its own 0.25-micron Diplomat-25 libraries as the foundation of customer-owned tooling (COT) solutions. According to the companies, the agreement will allow COT customers to create complex system-on-chip designs with Virtual Silicon's Diplomat-25 standard cells, I/Os and memories targeted to Amkor's technology process. Under the terms of the agreement, Virtual Silicon's Diplomat-25 cell-based libraries are available immediately for initiating chip designs. Amkor will accept prototypes in the third quarter; production is scheduled for early fourth quarter. The companies said a test chip is under way to verify the Diplomat-25 design rules, provide timing correlation, validate I/O performance and reliability, and finalize tooling procedures. Virtual Silicon also announced a marketing and technology partnership with NEC, in which the two companies have agreed to jointly develop and market an advanced cell-based, foundry-portable technology that will enable key customers to gain early access to NEC's recently announced 0.18-micron CMOS process. According to the companies, the joint solution will target high-complexity system-on-silicon customers in the consumer, communications and high-performance graphics markets. The companies said Virtual Silicon will deliver standard cells and memory compilers to both NEC and their key customers, while NEC will support customers via a complete physical design environment that includes access to physical libraries and embedded cores. Taiwan Semiconductor Manufacturing Co.(TSMC) has announced a silicon-verification test-chip program for library, IP and EDA vendors. According to the company, the purpose of the TSMC Silicon IP program is to provide TSMC's partners with slots for their own test chips on leading-edge technology mask and wafer lots. Chips from these wafers are delivered back to each vendor for their own analysis. These wafer lots will be run regularly by TSMC. The company further announced that it has solidified partnerships in the program with 14 vendors. They are Artisan Components, Aspec Technology, Avant!, Duet Technologies, Galax!, IMS, Leda Systems, Mentor Graphics, NurLogic Design, Silicon Access, Silicon Architects of Synopsys, Simplex Solutions, Virage Logic and Virtual Silicon Technology. TSMC is now making 0.25-micron CMOS wafers incorporating these vendors' test chips. Test-chip results and data will be available for customers in the second half of this year. 
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