W hen it comes to Merced, despite the engineering community's clamor for more information, Intel has imposed a virtual news blackout.

Last October, Intel provided a rough--very rough-- outline of the architecture at the Microprocessor Forum. Company executives also said that Merced is scheduled to ship in 1999 and that it will be fabricated in a 0.18-micron CMOS process.

No additional details emerged until last week, when Intel briefed EE Times and revealed that Merced will use a new system bus , using concepts from the Pentium II bus.

But the discussion shed little light on the inner workings of speculation and predication--the two code-optimization mantras upon which Merced and Intel's highly parallel IA-64 architecture are based.

For the uninitiated, IA-64 uses a technique called "explicit parallelism," which relies on a new kind of cooperation between processing hardware and software compilers. That combo is designed to deliver the performance benefits of a very-long-instruction-word architecture without the programming headaches usually attributed to VLIW.

Boiled down to its barest essentials, and rendered in plain English insofar as that's possible, predication removes branches from code by executing in advance both pre- and post-branch instructions at the same time. Then, the results from instructions that aren't "really" executed--that is, the branches th at aren't taken--are thrown out.

Speculation masks memory latency by yanking "load" instructions out of their normal place in the middle of a branch, and brings them forward to be initiated as early as possible in the flow of a program.

There's just one problem. Making predication and speculation work in the real world requires compilers several orders of magnitude more complex than anything in common usage today. So far, the two techniques have been tested only in research settings.

This knowledge should give everyone connected with Merced pause, because IA-64 is the first microprocessor architecture for which software (i.e., the compilers) will be more important than the silicon itself,

Not that the hardware won't be challenging. Intel's engineers will have their plates full trying to get Merced through the company's fab lines by its self-imposed shipment deadline of 1999. Intel executives won't say whether the chip has taped out yet, nor will they confirm when first silicon or samples will be available.

Once its production lines are rolling, Intel will have a hard time keeping up the yields. Merced is more complicated than anything Intel has ever made. Add to that the fact that it will be fabricated in a new, 0.18 micron process that hasn't yet been stressed to the max, and it's clear it will be some time before Intel is getting enough good wafers--and enough good die per wafer--to both satisfy demand and make a profit.

Such potential stumbling blocks aside, sources in the industry report that Intel is telling OEMs they can expect Merced samples in the second half of this year. If Intel really believes it can meet this deadline, then the company is further along with Merced than previously thought. (The other possibility is that Intel won't make its target, and will slip the sampling date into 1999.)

Indeed, Intel already appears to be tuning its dates a little. A company spokeswoman told me that shipments are slated for "the second half" of 1999. And alt hough systems OEMs have implemented engineering schedules in expectation of getting Merced samples this year, they won't die of shock if Intel doesn't pony up parts until early next year.

Despite Intel's shifting target, systems OEMs don't have the luxury of waiting. They're already hard at work designing Merced-based servers and workstations, in expectation of those Merced samples.

Hewlett-Packard, for one, is in the midst of a yeoman effort to engineer a family of Merced boxes code-named "Tahoe."

HP doesn't have hardware prototypes yet, because they don't have the Merced samples in hand. But Tahoe systems are being simulated in software. In addition, HP is porting software to HP-UX 11.0, a 64-bit version of the Unix-compatible OS that HP launched last November. Because HP-UX 11.0 is Merced-ready, it may have a jump over the upcoming 64-bit release of Windows NT as the OS of choice for the I ntel chip.

Even more impressive is the news that HP is rolling its own core-logic chip set for Merced. HP calls the chip set CEC, for core electronics complement. The objective is to give HP some technology to enable its Tahoe boxes to stand out from the many competitors which will also be equipped with the Merced CPU.

One big step HP is taking is to fold support for 16-way and 32-way multiprocessing into CEC. That could put HP at the front of the pack, since early word is that Intel is focusing its systems-engineering efforts on 8-way (and possibly 16-way) multiprocessing.

Taking off my reporter's hat and stepping into my role as a columnist, I have to say it's good to see HP out front with Merced. HP has rightly been revered for the strength of its engineering. Too often, however, HP hasn't garnered the kind of publicity it deserves.

With IA-64, for example, HP has been overshadowed by Intel. HP and Intel began working together on IA-64 back in 1994. The official line is that Intel and HP jointly developed the IA-64 instruction set, while Intel is building Merced on its own.

True, Intel is biting off a lot in its bid to ready Merced samples in a timely fashion. But I believe that HP, which has the software expertise required to make speculation and predication work, will remain more important to the future of IA-64 than anyone has acknowledged.

Let's wish them both luck.

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