M aking book on Merced could become my full-time occupation. Last Wintel Watch , I weighed in with some inside dope on the upcoming 64-bit microprocessor from Intel.

I opined that Intel will have its hands full getting the yields up on the new, 0.18-micron CMOS process in which Merced will be fabricated. I noted that Merced's companion software compilers will be far more complex than anything in use today. And I said that Intel's plan to ship Merced in the second half of next year may be subject to delay.

It turns out that Intel disagree s with some — well, with many — of the things I said. Since the folks at Intel are always gracious enough to return my calls when I pester them for technical information, I thought it would only be fair to let them respond with their take on the issues at hand.

I talked with Ron Curry, who is Intel's director of marketing for Merced. He took particular issue with my characterization of predication and speculation — the two techniques used to enable parallel processing inside of Merced — and my comment that compilers have so far tried these things out only in research settings, not the real world.

"We don't believe that that's the case," Curry told me. "Yes, you need to have a sophisticated compiler, but the compilers for today's superscalar architectures are already very complex. We have a few tricks up our sleeve, but this isn't compiler technology that had to be invented from the ground up to take advantage of Merced."

Curry added that Intel's Merced compilers are already being field tested. "We've had Windows NT and a number of applications recompiled and running on our simulator for some time," he explained. "There are a number of independent software vendors [ISVs] as well as operating-system vendors that are using our compiler."

Turning to the fabrication question, Curry claimed I was off base in saying that Intel will have trouble getting the Merced yields up. But he conceded that fabricating the 0.18-micron processor will be a challenge. "This is not any different than any new microarchitecture we've introduced," he said. "We're trying to mold the latest logic technology and the latest silicon technology. Of course we have a learning curve. But it's no different than what we did with Pentium, Pentium Pro, or Pentium II. We don't think there's any particular thing that makes Merced different, which we haven't been able to handle before."

As for the shifting ship dates, Curry noted that schedules tend to wiggle around a bit, especially when the planned launch is 18 months hence. But he said that Intel hasn't made any big changes in its schedule and expects to have first silicon this year.

For intrepid Merced observers, this means it's high time to begin learning the new IA-64 instruction set implemented by the processor. All the key OEMs and ISVs have already received — under tight nondisclosure restrictions — the Merced programmer's reference which lists the instructions. Publicly, though, Intel isn't talking until late this year or early 1999.

Curry wouldn't give me any details, though he did reveal that Merced will contain "functional equivalents" of the upcoming, second-generation MMX instruction-set extensions.

Before we get bogged down in jargon, we need a time out to deconstruct Intel's Kremlinesque MMX terminology. Intel's first generation of MMX instructions consists of 57 opcodes, which speed multimedia applications by enabling programmers to process many chunks of data in parallel. The second generatio n of MMX encompasses 70 additional floating-point instructions intended to accelerate 3-D processing. However, these new instructions aren't being called MMX. Instead, they're being dubbed "Katmai NI," for "Katmai new instructions," after the 32-bit Katmai CPU , which will be the first chip to include the opcodes when it debuts next year.

According to Intel's Curry, the 64-bit incarnations of the Katmai NI instructions will enable Merced to deliver about 20 times the performance of a 200-MHz Pentium Pro on 3-D applications.

Before signing off, Curry and I tackled the question of core logic. I have previously reported that Hewlett-Packard is developing a heavy-duty chip set which will support 32-way multiprocessing with Merced.

"One thing I want to clarify is that Intel and HP aren't the only ones making core-logic chip sets," Curry said. "We're engaged with quite a few companies, including Compa q, NEC, Sequent, Siemens-Nixdorf and others. I could list 20 OEMs that are doing Merced designs and many of them are also doing their own chip sets. So don't be surprised if you see multiprocessing systems that are 8-way, 16-way, or greater, from a number of vendors."

From my perspective, Curry provided valuable insight into Intel's thinking. It's clear the company is well aware of the many, complex issues involved in fielding the new, 64-bit processor architecture. It's also apparent that a tough road lies ahead.

What's your take on Merced? Send me your comments .

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