The second most interesting secret under lock and key at Intel Corp. (after the architecture of Merced) is the master list of its "Katmai New Instructions" (KNI). Intel isn't talking, but my sources have turned up some interesting information.

Katmai is the advanced 32-bit processor, due next year, that incorporates 70 special floating-point instructions to accelerate 3-D processing. Some saw these as "MMX2," a follow-on to the original 57 Pentium multimedia instruction-set extensions. But earlier this year Intel said the 70 instructions would officially be named KNI.

Some programmers have received KNI briefings from Intel under strict non-disclosure restrictions. But public information isn't available, so most of us remain in the dark.

Earlier this year, independent programmer Clive Turvey uncovered the first technical details of KNI and posted the news on his web site. He found that KNI includes a rich complement of add, compare, divide, prefetch and move operations, along with a set of floating-point MMX registers, XMM0 through XMM7, which are separate and distinct from the integer registers MM0-7.

Now, an industry analyst who wishes to remain anonymous has passed along some additional Katmai insights.

First off, he reports that the XMM registers are 128 bits wide. For the single-instruction, multiple-data paradigm implemented by MMX to be useful, four items must be calculated simultaneously. Therefore, each floating-point value will be 32 bits wide. Most significant is my source's report that the syntax of most of the KNI core instructions is the same as for the original MMX instructions. A sampling of some of the KNI instruction mnemonics turns up the following: addps, addss, cmpeqps, cmpordps, comiss, cvtpi2ps, divps, maxps and subps. (SS and PS are two new sets of registers. SS instructions have a single-byte prefix.)

Also of note is the news that Microsoft's DirectX 6 doesn't contain any Katmai code, according to my source. But it does take liberal advantage of the 3DNow multimedia instruction-set extensions from AMD.

Intel has said that Katmai will ship in 400- and 500-MHz versions. My source believes a 533-MHz part will also be available, with 1 Mbyte of L2 cache and a 133-MHz front-end bus. That's double the cache of the slower speed grades, with a 33 percent boost on the bus. A final wrinkle: A second class of Katmai (call it a Celeron) will use fast SDRAM instead of pipeline-burst SRAM as the L2 cache.