Thanks to some sources in the know, I've come into additional information on the inner workings of Intel Corp.'s upcoming 64-bit Merced microprocessor. This week, we'll take a look at speculation and related matters; other areas will be covered in future columns.

Merced will usher in a new kind of cooperation between on-chip hardware and the compiler. Given its very-long-instruction-word (VLIW) heritage, Merced will contain a large number of parallel execution units. In exchange, the compiler will organize instructions into instruction streams that can be simultaneously executed.

To obtain those streams, the compiler will rely on two software techniques: predication and speculation. The former removes unneeded branches from a program; the latter masks memory latency by executing load instructions as early as possible.

However, there's a little mystery hidden within Intel's nomenclature. Intel has used "speculation" as an umbrella term. What Intel hasn't revealed is that Merced will implement two types of speculation: control and data.

What Intel has discussed to date is really control speculation. That is, it's the procedure by which instructions are moved up above the branch. Control speculation is a well-known technique and is broadly applicable; that is, lots of code can benefit from its use.

The second method, data speculation, is much harder. Data speculation essentially means that when a memory access is performed, the compiler is not sure whether the access is valid or not. An example might be moving one store instruction way above another store instruction.

Data speculation is less broadly applicable, but on those portions of code where it does work, it can deliver performance boosts of 20 to 30 percent. (A further complication is that there are two definitions of data speculation floating around; the kind I've described is the method according to the less-stringent definition.)

Merced is also fitted with specific features to speed the execution of tight inner loops-small blocks of code that are executed repeatedly. To that end, Merced will implement rotating registers, my sources tell me. This feature boosts the performance of inner loops by enabling Merced to use "software pipelining." Merced's branch instructions will also be outfitted to support these fast loops. And Merced will probably allow multiple, simultaneous writes to its registers.

Finally, a correction to an item in a previous column: Intel tells me that Katmai, (its upcoming, advanced 32-bit processor) will initially ship in 450-MHz (not 400-MHz, as I wrote last month) and 500-MHz versions.