It seems to this humble observer that the software for Intel Corp.'s upcoming, 64-bit Merced microprocessor is coming along more smoothly than the chip's hardware. That's the impression I got from a recent briefing on the company's new, high-speed emulator that supports the Merced instruction set.

Intel is providing the emulator to a select group of vendors in a bid to spur the development of IA-64 systems software and applications.

Just how much success Intel's engineers are having building Merced itself is another question. Intel officials refuse to comment on reports circulating throughout the technical community that implementing the processor in silicon has become a mighty challenging task. These officials insist that things are going swimmingly and that chip samples will be available in mid-1999.

When those samples do arrive, they will include some interesting architectural features. Last week, we discussed the inclusion of data speculation in Merced (see Sept. 21, page 55). This week, let's delve into Merced's memory hierarchy and scheduling model.

Merced will incorporate a memory hierarchy which is unusual in that it is visible to the compiler. (Compilers are crucial to Merced's operation because they decompose applications into instruction streams that can be executed by the chip's parallel functional units.)

To aid the compiler in its tough task, Merced will offer unparalleled memory flexibility. For store instructions, Merced's compiler will be able to specify into which cache the data should be placed. For load instructions, the compiler will be able to specify where data that a program is waiting for can be found in cache, as well as where data results should be deposited in the cache.

Another interesting architectural twist inside Merced is its support for two different scheduling methods: the "less than or equals" (LTE) and the "equals" (EQ) models. The LTE model is the standard-issue technique used by all current CPUs. Under LTE, the destination register of an operation is held open from the start of the operation until the value is delivered into the register.

Under the innovative EQ model, the value is delivered to the destination register at exactly the time it will be needed by the instruction, as determined by the expected instruction latency. Prior to that time, the register is free to be used by other operations.

With the EQ model, Merced's designers have come up with a novel way to provide additional breathing room by effectively freeing up some of the registers, at least some of the time.