The year's most important conference for engineers plugged into pace-setting trends in microprocessor design will take place next week in Dallas. I believe the meeting-officially known as the 31st annual ACM/IEEE International Symposium on Microarchitecture, and more popularly as Micro-31-will one day be remembered as a philosophical turning point.

That's because reduced instruction set computing (RISC) will officially get taken down a peg in the thinking of the industry's elite. Taking its place at the top of the queue will be instruction-level parallelism (ILP), which is the politically correct way to refer to very-long-instruction-word (VLIW) architectures.

Orthodox VLIW designs have essentially been discredited. However, dozens of hybrid approaches will flower in coming years under the banner of ILP.

This reality will be hailed at the conference by two significant keynote speeches. Dave Ditzel, chairman of closely held Transmeta Corp., will speak on "20 years of RISC with lessons for the future." As Ron Wilson recently reported, Transmeta thinks RISC can be speeded up by decomposing instructions into VLIW-like parallel streams.

The second keynote will come from Josh Fisher of HP Labs, widely considered the godfather of VLIW. With his mid-1980s company Multiflow, Fisher was part of the first wave of architects who tried to popularize VLIW but essentially failed. Now, however, time has caught up with the technology. Indeed, Fisher and his HP Labs colleagues have played an unacknowledged but crucial role in folding ILP concepts into Intel's IA-64 architecture.

Because the term VLIW became tainted by its poor commercial showing a decade ago, Intel eschews it in favor of its own acronym, EPIC (for explicitly parallel instruction computing). Call it what you will, the key challenge in realizing the concept's potential won't be in hardware. Instead, it will lie in the compilers that must funnel application software into parallel streams of executable instructions.

Intel and others have grappled with the problem, which revolves around optimizing complex code sequences, pulling branches forward and cutting memory latency. Though reassurances are being offered all around, I believe that high-performance, battle-hardened compilers are likely to take time to emerge. Indeed, I hear two leading CPU experts are poised to launch a VLIW (ILP?) compiler company to help with just such issues.

For more on Micro-31, check out http://www.acm.org/sigmicro/micro31/. See you in Dallas.