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DAC targets 45-nm design
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EE Times


MANHASSET, N.Y. — A special Management Day session during the upcoming Design Automation Conference (DAC) will again tackle the toughest chip design issues using 45-nm process technology.

DAC gets underway June 8, and the all-day Management Day session is scheduled for June 10. The fourth annual event includes presentations from seven executives from fabless companies and independent device manufacturers, including Intel, Qualcomm and ST Microelectronics.

They will provide their tradeoff analysis and decision criteria for dealing with issues like the move to new process technology nodes, optimizing for high-volume production and overcoming power constraints.

Among the speakers are:

  • Elinora Yoeli, vice president of Intel's Mobility Group, who will discuss key design challenges for Intel's 45-nm Atom low-power processor.

  • Philippe Magarshack, vice president of ST Microelectronics' central R&D lab, who will discuss 45- and 40-nm low-power design as applied to wireless multimedia SoCs.

  • Charles Matar, vice president of engineering at Qualcomm, who will detail challenges in designing new wireless SOCs using 45-nm process technology in low-power cellphones.

  • Andrew Chang, vice president for design technology at MediaTek will discuss the Taiwan chip maker's place and route strategy in designing a 65-nm chip.

  • Bob Pitts, 45-nm platform manager at Texas Instruments, will discuss how his team optimized a 45-nm design for a low-power digital baseband SoC.

  • Srinivas Nori, ASIC design manager for Xbox silicon development at Microsoft, will review design challenges posed by the Xbox 360 graphics processor.

  • Manuel D'Abreu, a director at SanDisk will discuss design specifications for high-volume production of flash memory.

    DAC will be held June 8-13 at the Anaheim Convention Center.



  • Related Links:

  • Viewpoint: Embrace platform-based design



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