ANAHEIM, Calif. — Cyclos Semiconductor Inc. announced a proof-of-concept processor implementation using its platform and standard-cell design flow. Cylcos said at the Design Automation Conference here that it is licensing both tools.

The project, code-named "Elizabeth," is a resonant- clocked implementation of the ARM926EJ-S processor. It also provides silicon validation of the resulting deployment of the resonant-clock platform in a standard-cell processor design while demonstrating the Cyclos design flow on industry standard IP.

Cyclos is a privately-held startup based in Berkeley, Calif., that pioneered resonant-clock design technologies for ultralow-power devices.

The Elizabeth project has been implemented using commercial EDA tools from Cadence, Mentor Graphics, and Synopsys along with the ARM Metro standard-cell library and memory compiler for standard 130-nm bulk silicon process technology.

The chip includes 16-Kbytes data/instruction caches and 32-Kbytes data/instruction tightly-coupled memories.

The Cyclos RCL Platform and Cyclify design flow are compatible with ASIC and SoC design flows. They can be used to design low-power, resonant-clock implementations of synchronous ASICs and SoCs without changes to their development and verification environments.

"This new development will ensure that our partners have access to the industry's first commercially available resonant-clock methodology," said Eric Schorn, ARM's vice president of marketing for the Processor Division.

Cyclos is also licensing its Cyclify backend design flow for resonant-clock ASIC designs. Cyclify can be used with synthesized designs with no changes to synthesized netlists or verification vectors, the company said.

The RCL Platform for low-power ASIC design targets applications in the embedded, mobile, medical and server markets with ultralow-power and low-electromagnetic-interference requirements. RCL has been verified in silicon in conjunction with the Cyclify design flow on 130-nm bulk silicon.