And unlike its rival on the island, UMC, the world's second largest foundry vendor, said that it is not pushing the next-generation 450-mm wafer size.

UMC (Hsinchu) has been ramping up 65-nm processes for some time, but it will shortly move into the 45- and 40-nm nodes. Like its foundry rivals, the company has pushed out its high-k and metal gate solution to the 32-nm node.

As of late, the company has been somewhat less vocal about its cutting-edge process technologies, as compared to IBM's ''fab club'' and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). "We're definitely not behind," said Lee Chung, vice president of the corporate marketing division at UMC.

Like TSMC--and reportedly Chartered Semiconductor Manufacturing Pte. Ltd.--UMC is developing a 45-nm process and will also provide a 40-nm ''half-step'' technology.

UMC's 45-/40-nm process is multi-level metal technology with copper interconnects and ultra low-k dielectrics. At that node, UMC's low-k technology will have a ''k effective'' value of 2.5, compared to 3.0 at 65-nm.

The company will also make use of immersion lithography at those nodes. Its 45-/40-nm processes are expected to move into initial production by year's end, Chung told EE Times at DAC.

UMC is also working on its 32-nm process, which is expected to be released at the end of 2010. The process will make use of high-k and metal gates, but the company declined to elaborate on the technology.

It is expected to ramp up its 45-/40-nm technology in Fab 12, a 300-mm plant that is located in the southern Taiwan city of Tainan. At least for now, UMC is not pushing for 450-mm fabs. In contrast, rival TSMC, as well as Intel and Samsung are pushing the industry towards 450-mm fabs, which are being targeted for the 2012 time frame.

"Today, 450-mm is not exciting," Chung said. "At 300-mm, there are so many [productivity improvements] you can do.''

Asked if he saw 450-mm fabs appearing in 2012, he said: "I don't believe it." The real problem is the equipment makers, which "are not excited" about moving towards the next-generation wafer size, he said.

Meanwhile, at DAC, UMC announced a number of alliances with EDA houses. Cadence Design Systems Inc. and UMC announced the availability of a Common Power Format (CPF)-based low-power reference design flow targeted to UMC's 65-nm process.

Synopsys Inc. and UMC announced the release of a low-power design reference flow supporting UMC's 65-nm technology. The new reference design flow includes RTL-to-GDSII design capabilities based on the Unified Power Format (UPF) standard.

Magma Design Automation Inc. and UMC announced the availability of a validated UPF-compliant low-power RTL-to-GDSII design flow that uses the UMC's 65-nm library. And not to be outdone, Extreme DA and UMC announced their collaboration on variation-aware IC design flows for 65-nm and finer process technologies.