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Mentor forms design-to-silicon unit
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EE Times


ANAHEIM, Calif. — Seeking to drive the integration of its three main platforms, Mentor Graphics Corp. has merged several offerings into a single design-to-silicon division.

The Calibre physical verification and design-for-manufacturing platform, Olympus-SoC place-and-route system and the Mentor design-for-test and yield learning products will be handled by the new unit.

"We're engaged with our customers on a day-to-day basis in their design labs and fabs to ensure the Mentor offerings truly resolve customer needs at each step," Joseph Sawicki, vice president and general manager of the new division said during the Design Auomation Conference here.

The recently acquired assets of the Ponte Solutions and NXP Semiconductors' Germany DFT technology will also be folded into the new division.

Philippe Magarshack, STMicroelectronics Technology R&D group vice president and general manager of central CAD and design solutions, said the European chip maker has been working with Mentor Graphics on successive process technology nodes. ST previously work with Sierra Design Automation before it was acquired by Mentor in June 2007. "We encouraged the integration of Olympus-SOC and Calibre technologies to address the increasing challenges we foresee at 32 and 22 nanometers," he said.

Mentor also outlined plans at DAC for integrating chip designs across the three implementation platforms. For instance, Olympus-SoC/Calibre LFD (Litho-Friendly Design), which is used to avoid lithography hotspots during routing, will be extended through further integration of Calibre models earlier in the floorplanning and routing process.






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