The process involves mechanically initiating and propagating a crack parallel to the surface of a silicon wafer and as such is does not involve any kerf losses. In this way, silicon foils with an area of 25 square centimeters and a thickness of 30 to 50 microns have been produced. The method makes use of industrially available tools such as a screen printer and a belt furnace.

Adding an ultra-thin wafer or foil of active silicon on top of a low-cost substrate could reduce the amount of high-grade silicon used in solar cells, IMEC said.

IMEC is pursuing a number of different ways to produce such foils of crystalline silicon at an acceptable cost. One of the promising methods is a lift-off process that only requires the use of a screen printer and a belt furnace; no ion-implanted or porous layer is needed.

A metallic layer is screen-printed on top of a thick crystalline silicon wafer, which is then annealed in a belt furnace at a high temperature. When the wafer cools, the mismatch of the thermal expansion coefficient between the metal and the silicon induces a stress field in the substrate. The stress field grows, initiating and propagating a crack in the silicon, close to and parallel with the surface. Next, the top layer of the silicon and the attached metal layer snap off from the parent substrate. The metal layer is removed from the silicon foil in a metal-etching solution, resulting in a clean and stress-free silicon foil. The substrate can be re-used to peel off further layers.

The process was demonstrated on both single- and ploycrystalline silicon, as well as on Czochralski-pulled (Cz) material with different orientations.

One of the resulting thin Cz foils was further processed into a solar cell using a heterojunction emitter process. The one square centimeter cell reached an efficiency of 10.0% percent, without back-surface passivation or intentional surface texturing. These preliminary results indicate that the quality of the material is largely preserved during the lift-off process, in spite of the large stresses involved. IMEC expects to reach much higher efficiencies with added surface passivation and texturing.

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