Soitec SA has rolled out a new class of substrates. And the SOI Industry Consortium said that Nvidia Corp. has joined the organization.

The consortium, which was formed in 2007, hopes to accelerate SOI technology in the market. Graphics-chip maker Nvidia brings the SOI Consortium membership to twenty three companies.

Other members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Leti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, TSMC, Tyndall Institute, UCL and UMC.

Meanwhile, France's Soitec has rolled out a new generation of advanced substrates. New solutions--such as ultra-thin top silicon and ultra-thin buried oxide (BOX)--give designers a choice of substrates for partially depleted (PD) and fully-depleted (FD) devices, including multi-gate transistor architectures.

The new generation of substrates is built on its 300-mm Unibond XUT+ wafer technology, which is currently shipping to leading customers for the PD 45-nm logic market.

''To make strategic choices for 32-nm and beyond, Soitec customers now have a full range of options at their disposal,'' said Paul Boudre, Soitec's COO, in a statement.

''This is a major advantage for IC design today,'' he said. ''In addition, CMOS process simplifications, and advanced SOI memory solutions--like single transistor body cell or ZRAM--result in a lower cost-of-ownership for SOI ICs.''

This new generation of substrates is based on its Smart Cut process. The top silicon layer of these wafers is available in thicknesses ranging from just 20 nm up to 110 nm, while the BOX can be as thin as 10 nm. Options are also available like high resistivity substrate and strained SOI.