ASML and Canon have expanded their respective scanner lineups, while Nikon tweaked its roadmap, as chip makers rethink their double-patterning strategies. But at this week's Semicon West, IMEC and JSR Corp. may have stolen the show by rolling out a new ''freezing'' technique in double-patterning lithography. The entities claimed to have found a simplified process using only one etch step to reduce the cost of double patterning.

The industry is gearing up for double-patterning--and for good reason: There are ongoing rumors that EUV will not be ready for the 22-nm node, meaning the technology has been pushed out to the 16-nm node or beyond. This also implies that chip makers may have to resort to 193-nm immersion lithography--with double-patterning techniques--for both the 32- and 22-nm nodes.

Double-patterning implies that the wafer must be exposed twice, thereby increasing lithography costs. Even within the double-patterning world, there are various and complex flavors of the technology: double-exposure; trench double-patterning; line double-patterning; litho-etch-litho-etch, spacer and others.

Each technology has its own set of trade-offs. The biggest concerns with double-patterning are cost and overlay, said Harry Levinson, manager of strategic lithography technology and fellow at Advanced Micro Devices Inc.

The DRAM, NAND flash and logic camps will continue to use single-exposure techniques for current-generation devices--until, say, the 45-nm node and perhaps beyond.

At the 3x node or perhaps before that, the NAND flash-memory crowd, which is pushing the leading-edge, is looking at using 193-nm immersion lithography--with a technology called ''spacer'' or self-aligned double-patterning. Some NAND flash players are already using this technology, reportedly including Hynix Semiconductor Inc. and IM Flash Technologies LLC, the Intel-Micron memory venture.

In the past, the DRAM camp was looking at the so-called litho-etch-litho-etch scheme. Now, the DRAM camp is reportedly ditching this scheme in favor of the spacer technology.

The logic crowd wants to avoid using double-patterning techniques, although that might be easier said than done in most cases. Logic chip makers may be able to push out double-patterning by restricting their design rules.

In any case, Nikon Corp. (Tokyo) tweaked its roadmap. Earlier this year, the company disclosed that it is developing two 193-nm immersion scanners for double-patterning applications, including the S611C and S620D.

The S611C was an early ''learning tool'' that was supposed to be shipped by year's end, according to Nikon. Nikon will not field the S611C. Instead, the company will integrate many of the features of the S611C in its current 193-nm immersion tool, dubbed the S610C.

The S620D is still on track. The machine is geared for 45- and 32-nm designs and is said to have a throughput of 180 wafers per hour. It is expected to be delivered in 2009.