The companies reported the development in a jointly authored paper at ISSCC in San Francisco.

Up to now, most FRAM designs have used a so-called 2T2C structure: two transistors and two capacitors are used differentially to improve the signal-to-noise ratio in the sense amplifiers used to detect stored data levels.

The problem with the 2T2C approach is that it has resulted in chip capacities staying stubbornly below the 1-Mbit level. However, the more space-efficient 1T1C structure suffers from a relatively high proportion of marginal cells.

A 1T1C memory cell needs a reference cell, and earlier approaches developed by Fujitsu and Ramtron have focused on using a dummy ferroelectric cell. The designers modified this approach to make it possible to reject marginal cells by referencing them to variable off-chip voltages during test.

The redundancy scheme is used to switch marginal cells out of the memory array and replace them with good cells. The designers decided to use ferroelectric cells as the 'fuses' to perform the switching.

To allow more cells to be replaced during testing, Ramtron's engineers developed a scheme that is more efficient than conventional schemes.

Conventionally, the cell regions are split into primary cells and redundant cells in up to equal numbers driven by column-select circuitry. A fuse map determines which column addresses need to be mapped to the spare. For maximum redundancy, the efficiency of the array drops to roughly 50 percent.

The Ramtron scheme has just one column of redundant cells for a set of columns. A data cell region encodes the address of the column for one cell that needs to be remapped in each row. To map a bytewide column, the technique needs three data cells and one redundant cell in each row.

The designers claim the die area penalty for a 512-row, bytewide block is 5.7 percent.

Chris Edwards is the editor of Electronics Times, EE Times' sister publication in the United Kingdom.

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