While the memory discussed at ISSCC is intended as a test vehicle and demonstrator of the technology, it is a complete memory chip with all the peripheral decoding circuits required to allow it to operate on a printed-circuit board.

The next MRAM from Motorola will be even closer to commercial design: an MRAM in a sub-0.2-micron CMOS process of about 4-Mbit capacity, said Saied Tehrani, MRAM program manager at Motorola Labs (Tempe, Ariz.).

That device, or a similar one, could sample to customers in 2003 with full production slated to begin some time in 2004, Tehrani said.

Motorola is making a play to create a leading position in next-generation non-volatile memory — a technology that could eclipse flash or ferroelectric memory — and Tehrani said his team is transferring into the Semiconductor Products Sector (SPS) of Motorola, which will sponsor the next round of development.

The current work was conducted under the auspices of Motorola Inc. corporate research, with support from the Defense Advanced Research Projects Agency. "We have the commitment from SPS to develop the technology," Tehrani said.

As well as retaining its state when power is removed, the one- transistor, one magnetic tunneling junction (1T-1MTJ) architecture has exhibited phenomenal endurance moving beyond 10 billion read-write operations, with no degradation in resistance. That means MRAM is likely to exceed the numbers achieved by flash and ferroelectric memory.

Reading does involve a current passing through the MTJ stack but accelerated testing has shown in excess of 10 years mean-time-to-failure, Tehrani said.

Together with its very fast read and write times — on the order of a few tens of nanoseconds — MRAM has small-sized memory cells.

"We think this is going to [be] better than ferro [ferroelectric memory] in terms of cell size. With flash, although MRAM tends to be a little larger in cell size, we don't need the charge pump [used to develop a programming voltage on flash] so we can be smaller overall," said Tehrani.

"With our 8-inch wafer 'lab-fab' in Chandler, Ariz., we are now able to take MRAM to smaller geometries, which allows us to drive to higher memory densities and higher performance," said Tehrani. "Once MRAM development is completed, we expect the transfer to manufacturing will be accomplished quickly."

"This is significant. It's a demonstration of something larger and more product-like than has been done before," said Bill Reohr, a member of the research staff working on MRAM at IBM's Thomas J. Watson Research Center (Yorktown Heights, N.Y.). "It's a much larger array, and now they are getting more than 70 percent yield in the array. It spells a lot of hope for the MRAM programs at IBM and Infineon," he said, speaking of the other two main centers of MRAM research besides Motorola.

The 256-kbit MRAM shown at ISSCC is organized in a 16-kbit-by-16 array, and it has measured read power consumption of 24 milliwatts at 3 volts, said Motorola. The company said the MRAM's fast read and write speeds combined with virtually unlimited read/write cycles and competitive cost could enable the technology to replace existing memories, such as flash chips and DRAMs. It could also replace all but the fastest SRAMs, said Motorola.

However, not all observers feel Motorola will have a clear run to market. One of the key layers in an MRAM is the tunneling barrier, which separates the two magnetic layers. Some observers said that the extreme thinness of that layer and difficulties in keeping it uniform could prevent MRAMs from entering commercial production.

Tehrani said the aluminum-oxide layer currently stands a 2-nanometer thickness and was not a problem in uniformity. Peter Naji, who presented the ISSCC paper, was asked a question on uniformity at the end of his presentation. His answer was that the thickness was uniform to within 5 percent to 6 percent.

Besides process uniformity, another hurdle facing Motorola is minimizing contamination due to exotic materials used in the MRAM.

"People in fabs worry about any material. Copper was a challenge, but we know how to handle these materials," said Tehrani. "Iridium manganese and iron-manganese used in a layer to pin the magnetic polarization is probably the worst."

"We're working at 0.18 micron. They may see more problems there," said IBM's Reohr. But I'm very encouraged by the Motorola work."

More ISSCC coverage.