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On-line Seminars
| October 2001 |
| 12-October-01 | iApplianceWeb and National Semiconductor | Rather than using processors designed for PCs, a new generation of processor architecture designed specifically for embedded devices is driving the integration and functionality, and reducing the end cost of iAppliances. This seminar dives in to a few of the trends behind these new processor designs, specifically the role of multicore processors, mixed signal system-on-chip solutions, and the evolving role of hybrid programmable logic in appliances. | 12:00 PM PDT | Click here to attend or to pre-register |
| 16-October-01 | Tektronix-Europe | The NetSeminar will give an overview of the pivotal concepts of BluetoothTM. Moreover, the seminar aims to offer solutions to some of the unique challenges presented to BluetoothTM developers, in particular the verification and debug of BluetoothTM protocols are discussed. | 5:00 AM PDT | Click here to attend or to pre-register |
| 17-October-01 | Mentor Graphics |
Success in the electronics industry hinges on producing high quality products and using cost-effective methods to do so. Test is a necessary part of IC production to avoid selling or shipping defective components. Costs related to test impact product development, manufacture, and product test. In this NetSeminar, a Mentor Graphics Design for Test specialist will explain how to dramatically reduce the cost of manufacturing test. Significant cost reduction solutions include test compression, built-in self test, use of low cost testers, automation of key DFT processes, and new technologies which dramatically lower the cost of test. | 11:00 AM PDT | Click here to attend or to pre-register |
| 24-October-01 | Synopsys | Today's SoCs consisting of complex hardware and software can no longer be designed & verified only with RT-Level methodologies. They are too slow (simulation) or not applicable for all project phases (emulation). SoCs need to be designed at the system level and the executable specification needs to be signed-off prior to detailed implementation. In this netseminar designers will learn how using a SystemC-based design flow can significantly cut their design cycles. | 6:30 AM PDT | Click here to attend or to pre-register |
| 24-October-01 | Synopsys | Rebroadcast - Today's SoCs consisting of complex hardware and software can no longer be designed & verified only with RT-Level methodologies. They are too slow (simulation) or not applicable for all project phases (emulation). SoCs need to be designed at the system level and the executable specification needs to be signed-off prior to detailed implementation. In this netseminar designers will learn how using a SystemC-based design flow can significantly cut their design cycles. | 11:00 AM PDT | Click here to attend or to pre-register |
| 25-October-01 | Synopsys | Rebroadcast of 10/24 event.
Today's SoCs consisting of complex hardware and software can no longer be designed & verified only with RT-Level methodologies. They are too slow (simulation) or not applicable for all project phases (emulation). SoCs need to be designed at the system level and the executable specification needs to be signed-off prior to detailed implementation. In this netseminar designers will learn how using a SystemC-based design flow can significantly cut their design cycles. | 7:00 PM PDT | Click here to attend or to pre-register |
| 30-October-01 | Synopsys | Smarter Verification with Coverage Netseminar: Verification throughput can be dramatically improved with coverage-driven simulation. This seminar will discuss the value of coverage and how to incorporate it into your current flow. Value comes from more guided, efficient test development and a more efficient use of resources for regression tests. A quick implementation example using Synopsys VCS, the leading verilog simulation tool will also be reviewed. |
11:00 AM PDT | Click here to attend or to pre-register |
| November 2001 |
| 07-November-01 | Synplicity |
ASIC synthesis can be a difficult task, particularly given limitations in human resources and time schedules. This webcast will discuss how to achieve the highest productivity ASIC synthesis for a design team. It will detail limitations in current approaches and how they can be overcome with Synplify ASICTM, particularly in area of runtime, timing closure, and training. The summary for this session will be a checklist that designers can use to review their own synthesis strategies to target areas for improvement. | 6:30 AM PDT | Click here to attend or to pre-register |
| 07-November-01 | Synplicity |
Rebroadcast - ASIC synthesis can be a difficult task, particularly given limitations in human resources and time schedules. This webcast will discuss how to achieve the highest productivity ASIC synthesis for a design team. It will detail limitations in current approaches and how they can be overcome with Synplify ASICTM, particularly in area of runtime, timing closure, and training. The summary for this session will be a checklist that designers can use to review their own synthesis strategies to target areas for improvement. | 11:00 AM PDT | Click here to attend or to pre-register |
| 09-November-01 | iApplianceWeb |
TBD | 12:00 PM PDT | Click here to attend or to pre-register |
| 12-November-01 | Mentor Graphics |
TBD | 6:30 AM PDT | Click here to attend or to pre-register |
| 12-November-01 | Mentor Graphics |
TBD | 11:00 AM PDT | Click here to attend or to pre-register |
| 15-November-01 | Texas Instruments |
TBD | 11:00 PM PDT | Click here to attend or to pre-register |
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