Sierra this week is rolling out Olympus-SoC, an IC placement and routing system that claims to address lithography variations and multiple-mode, multiple-corner timing closure within a high-capacity database. It doesn't have RTL synthesis, but it does present a direct challenge to the three providers of RTL-to-GDSII implementation systems — Synopsys Inc., Cadence Design Systems, and Magma Design Automation.

With the Mentor agreement, Olympus-SoC will interact with Mentor's Calibre Lithography Friendly Design (LFD) product to obtain data about lithography "hot spots" and lithography-unfriendly structures. Olympus-SoC will then modify the layout to fix these errors. Mentor and Sierra will also work together to develop next-generation routing rules.

Sierra was launched in January 2003, and the company rolled out its Pinnacle suite in 2004. Pinnacle is a physical synthesis toolset that includes floorplanning, placement, optimization, and global routing, along with concurrent multiple-mode, multiple-corner timing analysis.

According to Shankar Krishnamoorthy, Sierra CTO, three "discontinuities" are occurring at 65 and 45 nm: variation in lithography, variation in timing closure, and very large capacities. "All of the current place and route systems have architectures that are seven years old or older, and none were designed with these three discontinuities in mind," he said. "They're having to do a lot of incremental band-aid work to try and fix it."

Gary Smith, chief EDA analyst at Gartner Dataquest, characterized Olympus-SoC as the second announced 65/45 nm tool suite. "There is room for three tools," he said. "Magma has announced, now Sierra has announced. The market can't wait much longer. Power users are starting 45 nm designs."

Olympus-SoC is already in use at customer sites, Sierra claims, and is slated for production release later this year. Olympus-SoC customers include STMicroelectronics and Cisco Systems.

Olympus-SoC is built on top of the Pinnacle architecture. In addition to the new router, it adds a shape-based design rule checking (DRC) engine, and an extraction engine that's been enhanced to address thickness variations. It also features OptRoute, which allows "live" interaction between route-based variability optimization and detailed routing.

The new detailed router, developed in-house at Sierra, claims to combine the flexibility of shape-based routing with the speed of gridded routing. The router minimizes lithography errors in OPC, Krishnamoorthy said, by avoiding "wrong way routing" and using intelligent via placement. The detailed router runs on multiple-CPU workstations today, and will support distributed networks in the fourth quarter.

The collaboration with Mentor involves two phases, Krishnamoorthy said. In the first phase, Olympus-SoC will import errors detected in Calibre-LFD, and fix these problems during layout. "Another aspect of the partnership is to develop and deliver the next generation of routing rules," he said. "That will have a larger impact."

Jean-Marie Brunet, market development manager at Mentor Graphics, said a mutual customer was the driving force behind the collaboration with Sierra. "The goals are to develop not only a post-processing automatic fix of LFD rule violations, but also a preventative methodology that works within a router to reduce hot spot violations," he said.

Further information about Olympus-SoC is in an article in the print edition of this week's EE Times.