The Chain solution, which already supports the ARM AMBA AHB and APB buses, is said to offer power-dissipation and design-productivity improvements over traditional on-chip synchronous bus architectures.

Silistix (Manchester, England), a spin-out from an asynchronous logic research group at the University of Manchester, said the Chain interconnect fabric generated by its Chainworks design and synthesis tool suite is a self-timed, packet-based interconnect network that manages data flow between IP cores on a chip without being dependent on the edges of a system clock. Using Chainworks, designers can synthesize a self-timed Chain interconnect that interfaces with synchronous blocks of a system-on-chip (SoC), such as processors or peripherals, that are connected through compliant AMBA protocols, the company said.

Chainworks fits within existing EDA design flows and generates the interconnect fabric between the various IP blocks Silistix said. Chain stands for chip area interconnect.

"The ARM-developed AMBA bus protocol continues to be very widely used by SoC designers," said David Fritz, CEO of Silistix. "By extending support to include the AMBA 3 AXI interface, we are opening up new opportunities for designers to reap the power, performance and design-time advantages of chips that use our self-timed interconnect, particularly in [network-on-chip] applications."