According to Blue Pearl (Santa Clara, Calif.) Cobalt reduces the time required to achieve timing closure and improves quality of results by automatically generating false and multi-cycle path timing constraints.

The software quickly identifies false and multi-cycle paths in full chip designs and chip modules specified at the register-transfer-level (RTL) in synthesizable Verilog. It then automatically generates timing constraints in the Synopsys Design Constraint (SDC) format.

By generating all of the timing-exception constraints at the functional RTL level, the software eliminates optimization of paths that contribute little to design performance. It generates industry-standard SystemVerilog Assertions (SVA) and Property Specification Language (PSL) assertions that can be used to independently verify the generated constraints using third-party simulation and formal verification tools.

Cobalt Timing Constraint Generation runs on the Solaris, Linux, and Windows operating systems. A one-year, time-based license costs $75,000.