San Jose, Calif. -- An ad hoc group is trying to come to grips with escalating problems arising from a lack of standards for simulating chip interconnects as they scale up to 5 Gbits/second and beyond. The issue has pitted Cadence Design Systems Inc. and Mentor Graphics Corp. in a battle to gain support for competing solutions.

Two proposals are on the table at the Ibis Macromodeling Library Task Group. But, so far, neither has been demonstrated to be a clear winner.

"We need a new generation of EDA tools for serial links. Modeling is a particularly vexing problem that is a long way from being sorted out," said Todd Westerhoff, who leads a high-speed signal integrity group in the router division at Cisco Systems Inc.

A high-speed design architect at Mentor said existing tools will be able to address the issues. However, all sides agreed the problem is complex.

The industry is rapidly moving to a host of fast serial interfaces to link chips, boards and systems (see story, page 49). But somewhere between 3.125 and 6 Gbits/second, high-speed signals take a troubling turn. Chip makers must resort to increasingly complex techniques such as transmit pre-emphasis and receiver equalization to send and recover a clock and a signal.

Conventional testing methods using eye models on an oscilloscope are no longer useful when such techniques are employed. In addition, traditional transistor-level Spice models are not effective when traffic of as much as a million bits must be simulated to test the chip-to-chip links. Thus, chip makers are starting to develop their own homegrown environments in C or Matlab to create chip models that OEM customers can drop into their system simulations.

"This works well as long as you are only using one vendor's parts, but all the silicon vendors have their own tools and environments with chip models tied to them. They don't work together, and they have no interoperability with traditional Spice or Ibis modeling tools," Westerhoff said. "We haven't seen this sort of problem in EDA since the 1980s, when systems houses were developing their own homegrown tools."

The situation will only get worse as speeds increase. Chip makers expect to use an ever-more-complex array of standard and proprietary signal-conditioning and filtering techniques that exhibit different effects on different pc boards and cables. As they do, signals are already appearing on an oscilloscope as a closed eye.

"There is nothing you can measure. This is what we are headed into," Westerhoff said. "This is well beyond what anyone has done in signal integrity before."

So far, designers must simply tolerate more uncertainty than they would like in their models. But as speeds increase, they could be forced into building board-level prototypes to test interconnects--a move that would take a toll in both costs and time-to-market.

Cadence vs. Mentor
The holy grail is a single simulation approach suitable for high-speed designs that will adequately model the chip signals and the effects caused by the nuances of the board trace or cable between them. The approach should be one that any chip or EDA vendor can readily support while protecting proprietary silicon intellectual property (IP).