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Laker tool claims 10x boost in a/ms design productivity
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EE Times


SAN FRANCISCO — Claiming to boost analog/mixed-signal design productivity 10 fold while maintaining handcrafted layout quality, Silicon Canvas Inc. Thursday (July 20) introduced a new Laker layout product, Laker DDL.

According to Silicon Canvas (San Jose, Calif.), highlights of the new release include an intelligent schematic generator, auto static and dynamic constraint extractors, optional manual constraint editor and transistor level custom placer and shape-based custom router. Laker DDL automatically extracts constraints from a design netlist, simulation results and design properties and, based on these constraints, automatically generates layout through a built-in constraint-driven place-and-route engine, according to the company.

Silicon Canvas noted that the development of the methodology for analog design has not kept pace with that of its digital counterpart and is "primitive." But as product life cycles get shorter and time to market pressures mount, designers are searching for a more productive methodology, the company said.

Conventional schematic-driven layout achieves a certain degree of success within a very limited scope, Silicon Canvas said. Laker's customers have enjoyed productivity gain through the Laker SDL flow, the company said.

"Laker DDL eliminates the time consuming and error prone process of constraint preparation in the conventional constraint-driven flow," said Hau-Yung Chen, Silicon Canvas president. "Moreover, the unified schematic and layout DB together with our patented Magic cell device model and the flexible hierarchical manipulation capabilities delivers near hand-crafted layout quality."

Laker DDL is available immediately for Sun Solaris (32-bit and 64-bit), Linux (32-bit and AMD 64-bit), and HP (32-bit and 64-bit) platforms. U.S. pricing for the tool begins at $70,000 for a one-year time-based license, Silicon Canvas said.






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