As the Design Automation Conference opens this week in San Francisco, North American chip designers seem to be happier with EDA tools and vendors than they were one year ago. But as the "EE Times 2006 EDA Users Survey" shows, IC designers still have deep concerns about, and various problems with, nanometer chip designs.

The research, conducted online between May 10 and May 22, in fact comprises three distinct surveys, on the design of chips, field-programmable gate arrays and pc boards. EE Times readers and TechOnline subscribers in North America, Europe and Asia were solicited by e-mail and asked to complete one of those three modules (see box, page 30).

Some commonality was found across the three surveys and geographies. In general, design tool users are most satisfied with EDA technology and accuracy, and least satisfied with pricing,

licensing and interoperability. North American-based engineers who participated in the IC and FPGA surveys generally expressed more overall satisfaction than engineers in the 2005 surveys, which focused on North America.

The 2006 IC survey shows a move to finer process geometries, with 65-nm chips now in progress worldwide. Engineers in all geographies foresee increases in gate counts and clock speeds within two years.

Chip designers today are most concerned about functional verification and timing closure. But as feature sizes shrink, they expect that managing leakage current will become their biggest concern--even bigger than design-for- manu factur- ability (DFM).

Most Europeans and Asians acknowledged that their latest IC design project ran late, while in North America, nearly half of the most-recent projects were late. North American designers cited a mean cost of $15 million per chip design project. EDA tool budgets are relatively stagnant in North America but are rising in Asia.

One surprising finding is that only a minority of companies are outsourcing portions of chip design. And when they do outsource, they most frequently use companies in their own geographic region, although there's a growing trend for North American companies to go overseas.

Vendor usage and satisfaction ratings indicate that Cadence Design Systems Inc. has gained some ground in North America. Indeed, a geographical pattern can be discerned in respondents' vendor ratings: For many of the criteria, North American engineers most often favored Cadence, Europeans chose Mentor Graphics Corp. and Asians stuck with Synopsys Inc.

Geometry down, complexity up
The IC design survey included responses from 215 North Americans, 43 Europeans and 109 Asians, along with a few respondents who didn't indicate nationality. About half the Asians hailed from India, and most of the rest were from China or Taiwan. Most respondents described themselves as design engineers rather than managers, and companies of all sizes were represented.

In North America, 56 percent of current chip designs still use 0.13-micron or larger line widths, and 26 percent are at 90 nm. But 16 percent are at 65 nm, compared with just 5 percent in last year's survey, and 2 percent are already working at 45 nm.

In two years, 45 percent of North American designers expect to be working at 65 nm and below; of those, 18 percent expect to be working at 45 nm. European and Asian engineers are just slightly behind in their use of 65-nm technologies today, and their expectations two years out are less aggressive by a few percentage points.