The tool, CyberWorkBench, or CWB, is the result of C-based design tools developed by NEC's Central Research Laboratories. NEC started using the tools for chip design in 1999. In 2001, Matsushita started using the tools for ASIC and FPGA designs.

"One of CWB's advantages is that the solution has been used to design many LSI chips," said an NEC spokesman.

The design flow is done in the C language. While C-based design tools are thought by some to be ill-suited for design control circuits, CWB includes two algorithms for data processing circuits and control circuits. So it can design the whole LSI chip that integrates data processing and control blocks, which is another advantage, said the spokesman.

NEC estimated the C-based design tool market could be worth about $1 billion by 2010. It hopes to grab a 10-20 percent stake in the new market from leaders Cadence, Mentor and Synopsys.

NEC will exhibit CWB at the Design Automation Conference 2006 in San Francisco next week (July 24-27). It will also begin shipping a beta version next week.

The product version of the CWB tool is scheduled to begin in September. An annual license for the minimum configuration is priced at about $300,000.