The environment includes a statistical timing analyzer developed by Fujitsu, along with cell libraries that are characterized for process variations. This characterization is handled by the Anova Suite, a tool set for process variation measurement and cell library characterization introduced by Anova Solutions Inc. earlier this month.

According to Fujitsu, standard static timing analysis can overestimate circuit delay. Statistical timing analysis promises to more accurately model delays caused by process variations.

"Our COT and ASIC customers want to use this technology for their processors, graphics and high-end network ICs," said Tsuyoshi Yamamoto, senior manager for SoC development at Fujitsu Microelectronics America. He said that customers can gain 6 percent higher frequency with 30 percent less timing optimization by using Fujitsu's statistical timing environment.

While third-party statistical timers are available, Fujitsu chose to use its own tool because commercial tools can't accurately read Anova's statistical library at this time, Yamamoto said.

ASIC and COT customers will use the statistical analysis tool for critical paths that are influenced by process variations. Fujitsu does not plan to sell the tool. Fujitsu's statistical timing environment will be available on October 2006 for the 90 and 65 nm process nodes.

Fujitsu is not exhibiting at DAC, but will discuss its statistical timing environment at panel sessions, a spokesman said.

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