Opening up the Design Automation Conference here, Bryan Lewis, vice president of semiconductor research at Gartner Dataquest, a market research company. He estimated the structured-platform ASIC market will be about $417 million in 2006, down from his earlier forecast of $473 million. The market could still grow to $564 million in 2007 and to just over $1 billion in 2010, said Lewis.

Although sales of structured devices are increasing, the percentage as part of the total ASIC market will decrease to just 3 percent of a $30 billion market, he added.

Each design start will encompass much more logic than in past years. In 1995, for example, advanced design features were at 0.35 microns and designers were able to achieve chip complexities of 2.5 million gates. In 2005, leading-edge designs were at 65 nm and chip complexities of 100 million gates were achievable.

By 2010, features will shrink to 32 nm and designers should be able to cram over 500 million gates on a chip, Lewis estimated. By 2015, a new approach to design, referred to as restrictive design rules (RDR) will be required to deal with the impact of designing with features below 32 nm.

Due to issues related to design-for-manufacturing rules, the idea of restricting what the silicon designers can do will help improve the chances that designs will work the first time through the fabrication process.

One change likely to be wrought by RDR is the use of robust programmable platforms—chips like Philips' Nexperia, OMAP and DaVinci from Texas Instruments and the Uniphier from Panasonic. With hardware predefined, software configures the chip to define its system function. Such platforms will be expensive to develop, with Philips and TI investing close to $1 billion each, according to Lewis.